[PATCH 1/4] clk: meson: g12a: fix fclk_div2p5 multiplier

[Ronald Claveau via B4 Relay]

From: Ronald Claveau <linux-kernel-dev at aliel.fr>

g12a_fclk_div2p5 should be fclk divided by 2.5.
The mult has been declared as 1 which results
as fclk/5 instead of fclk/2.5.

Set mult=2 to get the correct div 2.5 rate.

Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Ronald Claveau <linux-kernel-dev at aliel.fr>
---
 drivers/clk/meson/g12a.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index d0d4c7b6dc82..4ec5f15daf98 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -995,7 +995,7 @@ static struct clk_regmap g12a_fclk_div7 = {
 };
 
 static struct clk_fixed_factor g12a_fclk_div2p5_div = {
-	.mult = 1,
+	.mult = 2,
 	.div = 5,
 	.hw.init = &(struct clk_init_data){
 		.name = "fclk_div2p5_div",

-- 
2.43.0