[PATCH v1] KVM: arm64: pkvm: Clear GICv3 LRs in the hypervisor

[Fuad Tabba]

Hi Vincent,

On Wed, 21 Oct 2026 12:00:00 +0100, Vincent Donnefort
<vdonnefort at google.com> wrote:
> The LR registers are architecturally UNKNOWN when the CPU boots or
> resumes. However, in protected mode, only the used ones are reset.
[...]
> Cc: stable at vger.kernel.org

Could you say in the commit message what happens to a guest when an LR
isn't cleared? It's what justifies the Cc: stable.

I tested it with QEMU modified to leave a chosen value in the top LR
at every CPU reset. Without the patch, the guest took a spurious
interrupt when that LR held a pending interrupt. When the LR had only
its EOI bit set, the EOI maintenance interrupt stayed asserted while
the guest ran, and the guest didn't print anything in 150s. With the
patch, neither happened.

With the commit message updated:
Reviewed-by: Fuad Tabba <fuad.tabba at linux.dev>
Tested-by: Fuad Tabba <fuad.tabba at linux.dev>

Cheers,
/fuad