[PATCH 2/2] arm64: Apply existing Apple CPU workarounds to M3 and M4

[Yureka Lilian]

On 10/9/26 10:16, Marc Zyngier wrote:
> On Fri, 09 Oct 2026 01:03:57 +0100,
> Michael Reeves <michael.reeves077 at gmail.com> wrote:
>>> I can provide the binary (and a few scripts) to test this easily.
>>> Should they have been fixed, we can always create a second
>>> implementation list to cover the PMU.
>> Can you please send that so we can try? That would be much
>> appreciated, thank you.
> I've sent you (and Yureka) details over IRC. If you need help with
> setting things up, let me know directly.
>
> Thanks,
>
> 	M.


Hi all,


sorry for the long delay on this. I needed to get my testing setup in 
shape to be able to run the tests with the limited amount of I/O I have 
working on these devices.
But I can now confirm, that the following SoCs reproduce the SEIS 
erratum (produce a host SError using the binary sent by Marc) unless the 
MIDR part numbers are added to the has_broken_gic_v3_seis list.

The affected SoCs are:
- T8132 (M4)
- T8140 (A18 Pro)
- T6050 (M5 Pro)

So please add those to the list for v2 of this series, and probably also 
add T604x (M4 Pro/Max) and T8142 (M5) since I doubt they will be different).


Thanks,

Yureka