[PATCH 3/4] arm64: insn: operate on MSR/MRS sysreg field via defines
Vladimir Murzin
vladimir.murzin at arm.com
Tue Oct 20 03:12:23 PDT 2026
On 10/16/26 17:46, Ada Couprie Diaz wrote:
> Replace the few instances of hard-coded system register offset and masks
> used to operate on MSR/MRS instructions with defines.
> This will allow re-use in future commits while making the connection
> between those values more explicit.
>
> While we are here, mark `aarch64_insn_extract_system_reg()` `noinstr`
> so it can be safe to use in alternative pacthing callbacks.
>
> Signed-off-by: Ada Couprie Diaz <ada.coupriediaz at arm.com>
> ---
> arch/arm64/include/asm/insn.h | 3 +++
> arch/arm64/lib/insn.c | 8 ++++----
> 2 files changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index 2e45f6e80d15f..e020f9d8b83c2 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -113,6 +113,9 @@ enum aarch64_insn_register {
> AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */
> };
>
> +#define AARCH64_INSN_SYSREG_OFFSET 5
> +#define AARCH64_INSN_SYSREG_MASK GENMASK(20, AARCH64_INSN_SYSREG_OFFSET)
> +
> enum aarch64_insn_special_register {
> AARCH64_INSN_SPCLREG_SPSR_EL1 = 0xC200,
> AARCH64_INSN_SPCLREG_ELR_EL1 = 0xC201,
> diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
> index 94ee1aae2f5b7..2edc5a9c0a9c8 100644
> --- a/arch/arm64/lib/insn.c
> +++ b/arch/arm64/lib/insn.c
> @@ -1362,9 +1362,9 @@ u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset)
> /*
> * Extract the Op/CR data from a msr/mrs instruction.
> */
> -u32 aarch64_insn_extract_system_reg(u32 insn)
> +noinstr u32 aarch64_insn_extract_system_reg(u32 insn)
> {
> - return (insn & 0x1FFFE0) >> 5;
> + return (insn & AARCH64_INSN_SYSREG_MASK) >> AARCH64_INSN_SYSREG_OFFSET;
> }
>
> bool aarch32_insn_is_wide(u32 insn)
> @@ -1566,8 +1566,8 @@ u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
> {
> u32 insn = aarch64_insn_get_mrs_value();
>
> - insn &= ~GENMASK(20, 5);
> - insn |= sysreg << 5;
> + insn &= ~AARCH64_INSN_SYSREG_MASK;
> + insn |= sysreg << AARCH64_INSN_SYSREG_OFFSET;
> return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
> insn, result);
> }
> -- 2.43.0
>
FWIW,
Reviewed-by: Vladimir Murzin <vladimir.murzin at arm.com>
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