[PATCH 1/2] dt-bindings: interrupt-controller: gicv5: Relax IRS properties constraints

[Lorenzo Pieralisi]

On Thu, Oct 15, 2026 at 10:20:25AM +0200, Lorenzo Pieralisi wrote:
> An IRS is architecturally allowed to be stand-alone (ie with no direct
> CPU connection).
> 
> Relax "cpus" and "arm,iaffids" properties constraints allowing a standalone
> IRS configuration.
> 
> Fixes: 7d7299bd07c6 ("dt-bindings: interrupt-controller: Add Arm GICv5")
> Signed-off-by: Lorenzo Pieralisi <lpieralisi at kernel.org>
> Cc: Rob Herring <robh at kernel.org>
> Cc: Marc Zyngier <maz at kernel.org>
> ---
> I have not marked the patch for stable though I think it should go
> to stable kernels to fix the original schema. I am a bit nervous about
> making cpus and arm,iaffids optional but I don't think there is a way
> to keep them required and force them to be empty for an IRS with
> no CPU connection.

Hi Thomas, all,

I have noticed this is now queued into -tip (thanks), I would still appreciate
DT maintainers feedback though on the above and I still think that this must
go to stable kernels (I have not tagged the patches CC: stable as mentioned in
the cover letter but I believe the Fixes: tag will do ? If not I can send
them myself anyway).

Thanks,
Lorenzo

> ---
>  .../devicetree/bindings/interrupt-controller/arm,gic-v5.yaml     | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
> index 86ca7f3ac281..b901e4288816 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml
> @@ -120,13 +120,14 @@ patternProperties:
>  
>        cpus:
>          description:
> -          CPUs managed by the IRS.
> +          CPUs managed by the IRS. Omit it if the IRS has no associated CPUs.
>  
>        arm,iaffids:
>          $ref: /schemas/types.yaml#/definitions/uint16-array
>          description:
>            Interrupt AFFinity ID (IAFFID) associated with the CPU whose
>            CPU node phandle is at the same index in the cpus array.
> +          Omit it if the IRS has no associated CPUs.
>  
>      patternProperties:
>        "^its@[0-9a-f]+$":
> @@ -210,12 +211,14 @@ patternProperties:
>            - reg
>            - reg-names
>  
> +    dependencies:
> +      cpus: [ "arm,iaffids" ]
> +      arm,iaffids: [ cpus ]
> +
>      required:
>        - compatible
>        - reg
>        - reg-names
> -      - cpus
> -      - arm,iaffids
>  
>  additionalProperties: false
>  
> 
> -- 
> 2.53.0
>