[PATCH v2 10/24] dt-bindings: phy: Add ZTE ZX279128S PCIe PHY binding

[Krzysztof Kozlowski]

On Wed, Oct 14, 2026 at 08:20:50AM +0100, Navid Ghahremani wrote:
> Add Device Tree binding for the PCIe SerDes PHY found inside the
> topcrm block of the ZTE ZX279128S SoC.
> 
> Signed-off-by: Navid Ghahremani <ghahramani.navid at gmail.com>
> ---
>  .../bindings/phy/zte,zx279128s-pcie-phy.yaml  | 40 +++++++++++++++++++
>  1 file changed, 40 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml
> new file mode 100644
> index 0000000000..7bfa363294
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/zte,zx279128s-pcie-phy.yaml
> @@ -0,0 +1,40 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/zte,zx279128s-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ZTE ZX279128S PCIe PHY
> +
> +maintainers:
> +  - Navid Ghahremani <ghahramani.navid at gmail.com>
> +
> +description:
> +  PCIe PHY block inside the ZTE ZX279128S Top CRM.
> +
> +properties:
> +  compatible:
> +    const: zte,zx279128s-pcie-phy
> +
> +  reg:
> +    description: Port index (0 or 1)
> +    items:
> +      - enum: [0, 1]

No, that's pointless. What is this index meaning on the bus?

> +
> +  "#phy-cells":
> +    const: 0
> +

No other resources? Then this belongs to the parent node.

Best regards,
Krzysztof