[PATCH v2 3/5] arm64: dts: imx8qxp: Add MIPI-LVDS combo subsystems

[Frank Li]

On Wed, Oct 14, 2026 at 09:16:47AM +0200, Alexander Stein wrote:
> From: Liu Ying <victor.liu at nxp.com>
>
> The MIPI-LVDS combo subsystems are peripherals of pixel link MSI
> bus in i.MX8qxp display controller subsystem.  Add the MIPI-LVDS
> combo subsystems.
>
> Signed-off-by: Liu Ying <victor.liu at nxp.com>
> Signed-off-by: Alexander Stein <alexander.stein at ew.tq-group.com>
> ---
> Changes in v2:
> * None
>
>  .../boot/dts/freescale/imx8qxp-ss-dc.dtsi     |   4 +
>  .../dts/freescale/imx8qxp-ss-mipi-lvds.dtsi   | 443 ++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8qxp.dtsi    |   3 +
>  3 files changed, 450 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
> index 647ee3348f494..9916a06669c87 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-dc.dtsi
> @@ -156,10 +156,12 @@ port at 1 {
>
>  				dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint at 0 {
>  					reg = <0>;
> +					remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>;
>  				};
>
>  				dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint at 1 {
>  					reg = <1>;
> +					remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>;
>  				};
>  			};
>
> @@ -211,10 +213,12 @@ port at 1 {
>
>  				dc0_pixel_link1_mipi_lvds_1_pxl2dpi: endpoint at 0 {
>  					reg = <0>;
> +					remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link1>;
>  				};
>
>  				dc0_pixel_link1_mipi_lvds_0_pxl2dpi: endpoint at 1 {
>  					reg = <1>;
> +					remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link1>;
>  				};
>  			};
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi
> new file mode 100644
> index 0000000000000..67f5392cfc803
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-mipi-lvds.dtsi
> @@ -0,0 +1,443 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +#include <dt-bindings/clock/imx8-lpcg.h>
> +#include <dt-bindings/firmware/imx/rsrc.h>
> +
> +/ {
> +	mipi_lvds_0_ipg_clk: clock-mipi-lvds0-ipg {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <120000000>;
> +		clock-output-names = "mipi_lvds_0_ipg_clk";
> +	};
> +
> +	mipi_lvds_1_ipg_clk: clock-mipi-lvds1-ipg {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <120000000>;
> +		clock-output-names = "mipi_lvds_1_ipg_clk";
> +	};
> +};
> +
> +&dc0_pl_msi_bus {
> +	mipi_lvds_0_irqsteer: interrupt-controller at 56220000 {
> +		compatible = "fsl,imx-irqsteer";
> +		reg = <0x56220000 0x1000>;
> +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent = <&gic>;
> +		#interrupt-cells = <1>;
> +		clocks = <&mipi_lvds_0_lis_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "ipg";
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +	};
> +
> +	mipi_lvds_0_csr: bus at 56221000 {
> +		compatible = "simple-pm-bus", "syscon";
> +		reg = <0x56221000 0x1000>;
> +		clocks = <&mipi_lvds_0_di_mipi_lvds_regs_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "ipg";
> +		#address-cells = <1>;
> +		#size-cells = <1>;

Does any children nodes have address?

> +		ranges;
> +
> +		mipi_lvds_0_pxl2dpi: pxl2dpi {
> +			compatible = "fsl,imx8qxp-pxl2dpi";
> +			fsl,sc-resource = <IMX_SC_R_MIPI_0>;
> +			power-domains = <&pd IMX_SC_R_MIPI_0>;
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port at 0 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0>;
> +
> +					mipi_lvds_0_pxl2dpi_dc0_pixel_link0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&dc0_pixel_link0_mipi_lvds_0_pxl2dpi>;
> +						status = "disabled";
> +					};
> +
> +					mipi_lvds_0_pxl2dpi_dc0_pixel_link1: endpoint at 1 {
> +						reg = <1>;
> +						remote-endpoint = <&dc0_pixel_link1_mipi_lvds_0_pxl2dpi>;
> +						status = "disabled";
> +					};
> +				};
> +
> +				port at 1 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <1>;
> +
> +					mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0: endpoint at 0 {
> +						reg = <0>;
> +						remote-endpoint = <&mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi>;
> +						status = "disabled";
> +					};
> +
> +					mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1: endpoint at 1 {
> +						reg = <1>;
> +						remote-endpoint = <&mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi>;
> +						status = "disabled";
> +					};
> +				};
> +			};
> +		};
> +
> +		mipi_lvds_0_ldb: ldb {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			compatible = "fsl,imx8qxp-ldb";

compatible should be first property, check others

> +			clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>,
> +				 <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
> +			clock-names = "pixel", "bypass";
> +			assigned-clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>;
> +			assigned-clock-parents = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>;
> +			power-domains = <&pd IMX_SC_R_LVDS_0>;
> +			status = "disabled";
> +
> +			channel at 0 {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				reg = <0>;

reg should be first one.


Frank