[PATCH RFC 3/5] dt-bindings: reset: Describe the BCMBCA PMB reset controller

[Philipp Zabel]

On Mi, 2026-10-14 at 11:48 +0200, Linus Walleij wrote:
> Describe a reset provider below the Processor Monitor Bus (PMB)
> controller, which owns the register bank and serializes accesses.
> Use one specifier cell for a SoC-specific logical reset group ID.
> 
> Define BCM6846_RESET_XRDP for the coordinated reset of the XRDP packet
> engine and its three Runner cores. The vendor PMB device addresses
> identify individual blocks, not this group, so assign it reset ID 0.
> 
> Define separate IDs for PCIe0 and PCIe1 soft resets and PVTMON analog
> acquisition. Describe the scope and prerequisites of each operation.
> 
> Use only the SoC-specific compatible because the reset groups and PMB
> interfaces differ between BCMBCA SoCs. There is no common reset
> contract for a family-wide fallback compatible.
> 
> Assisted-by: LLM
> Signed-off-by: Linus Walleij <linusw at kernel.org>
> ---
>  .../bindings/reset/brcm,bcm6846-pmb-reset.yaml     | 46 ++++++++++++++++++++++
>  include/dt-bindings/reset/brcm,bcm6846-pmb.h       | 15 +++++++
>  2 files changed, 61 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm6846-pmb-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm6846-pmb-reset.yaml
> new file mode 100644
> index 000000000000..c8a1e5132fa5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/brcm,bcm6846-pmb-reset.yaml
> @@ -0,0 +1,46 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reset/brcm,bcm6846-pmb-reset.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Broadcom BCMBCA Processor Monitor Bus reset controller
> +
> +maintainers:
> +  - Linus Walleij <linusw at kernel.org>
> +
> +description: |
> +  The Processor Monitor Bus (PMB) provides access to reset registers in
> +  BCMBCA SoC blocks. Each reset specifier identifies a logical reset group,
> +  which may span several blocks that must be reset together. Blocks must
> +  be powered and all affected users quiesced before requesting a reset.
> +
> +  BCM6846_RESET_XRDP covers the XRDP packet engine and three separate Runner
> +  cores. All participating blocks are asserted before any is released.
> +  The bus interfaces remain accessible throughout the reset.
> +
> +  BCM6846_RESET_PCIE0 and BCM6846_RESET_PCIE1 pulse the PCIe PMB soft
> +  resets, including IDDQ, while preserving the lane-selection straps.
> +  These are separate from PCIe PERST and the controller-local resets.
> +
> +  BCM6846_RESET_PVTMON resets analog acquisition in the process, voltage
> +  and temperature monitor. Its clock and power configuration are retained.
> +  Users must coordinate with any firmware performing voltage monitoring.
> +
> +  This node is a child of the PMB controller in the third generation
> +  Platform Management Controller (PMC3), which owns the shared register
> +  bank and serializes access to its keyhole interface.

Why is this a separate child node instead of just #reset-cells property
on the PMB node?

regards
Philipp