[PATCH RFC 00/24] ARM: zte: Add support for Sanechips ZX279128S and ZTE ZXHN H3600

[Navid Ghahremani]

Hi Stefan,

Thank you for the candid feedback, and I completely understand your
concern.

To be completely honest, I am returning to low-level C and kernel systems
work after being on the software/application side for quite a few years.
This router bring-up is a personal hobby project that I work on in my
spare time rather than my daily job, so I am a bit slow right now and
still catching up to speed with modern kernel architecture conventions.

All my work is done directly on physical ZTE ZXHN H3600 hardware on my
desk with serial UART, netbooting over TFTP, and live devmem probing.
While I initially relied on ZTE's vendor BSP to identify register bases
and magic bit offsets, I agree that several parts had a vendor code smell
that needed to be dismantled.

In v2, I took your feedback to heart to clean this up:
1. I eliminated the raw syscon poking in the PCIe controller entirely,
   isolating the SerDes and PLL into a proper Generic PHY driver
   (#phy-cells = <0>) under drivers/phy/zte/ and routing clocks via CCF.
2. I adopted your unified spi-zx.c driver with dynamic CCF clock rate
   scaling (clk_get_rate) and verified it on physical silicon with
   128 MiB SPI-NAND and UBIFS.
3. I split the CRM bindings into dedicated topcrm and lspcrpm schemas,
   moved the reboot node under topcrm with simple-mfd, and replaced raw
   register offsets in the reset bindings with sequential logical enum
   IDs (0, 1, 2...) in include/dt-bindings/reset/zte,zx279128s-reset.h.
4. I consolidated MAINTAINERS under ARM/ZTE ZX SOC SUPPORT with both of
   us as co-maintainers.

Regarding your observations on patch 07 (PLL reuse with pll-zx.c, the
32 kHz clock origin, and a dedicated pinmux driver): you are spot on.
For this v2 baseline, I kept the clock driver scoped to the working
peripherals needed for solid platform boot and retained pinctrl-single
for the initial muxing. As I get more time on weekends, I would be very
glad to work with you on unifying the PLL code with pll-zx.c and
expanding pinmux coverage once this clean foundation is in place.

Thank you again for the patience, guidance, and collaboration!

Best regards,
Navid