回覆: [PATCH 1/3] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY

[Jacky Chou]

Hi Krzysztof

Thank you for your reply.

> > Introduce device-binding for ASPEED AST2600/2700 PCIe PHY.
> > The PHY provides the physical layer used by the PCIe controller when
> > operating in root complex mode.
> >
> > Describe the compatible strings, register range, clocks and phy-cells
> > value required by the PHY provider.
> >
> > Signed-off-by: Jacky Chou <jacky_chou at aspeedtech.com>
> > ---
> >  .../bindings/phy/aspeed,ast2600-pcie-phy.yaml      | 49
> ++++++++++++++++++++++
> >  1 file changed, 49 insertions(+)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
> > b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
> > new file mode 100644
> > index 000000000000..686b2e3d9457
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.ya
> > +++ ml
> 
> What? v9 here:
> https://lore.kernel.org/all/20260115-upstream_pcie_rc-v9-1-d6c82a1556a7@a
> speedtech.com/
> from the same person, reviewed, but you ask us to do the same work second
> time? Really?
> 

I'm sorry again for the confusion caused by this submission and for asking reviewers 
to review work that had already been reviewed.

I plan to update this YAML binding in v10. Since the previous version received your 
Reviewed-by tag, could you please clarify what kinds of changes would require me to 
drop the tag and request a fresh review?
I'll document any changes to the binding in the cover letter's changelog.

Thanks,
Jacky