[PATCH v5 0/2] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

[Catalin Marinas]

On Sat, 10 Oct 2026 01:19:44 +0800, Peng Fan (OSS) wrote:
> This picks up the work originally done by Ivan T. Ivanov in 2023 [1],
> reworked to address review feedback from Will Deacon and Mark Rutland,
> and rebased onto linux-next (next-20261008).
> 
> According to NXP errata document IMX8_1N94W [2], the i.MX8QuadMax and
> i.MX8QuadPlus SoCs suffer from a cache coherency issue (ERR050104).
> The upper bits, above bit 35, of the ARADDR and ACADDR buses within
> the Arm A53 subsystem have been incorrectly connected, corrupting some
> TLBI and IC maintenance operations exchanged between the A53 and A72
> core clusters.
> 
> [...]

Applied to arm64 (for-next/cpu-errata), thanks!

I tweaked a few bits in here: commit, Kconfig and errata description
texts, some code comments.

[1/2] arm64: cpufeature: add ARM64_CPUCAP_SOC_ERRATUM for SoC-level errata
      https://git.kernel.org/arm64/c/cea68e7489a0
[2/2] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue
      https://git.kernel.org/arm64/c/d44e08dab27d