[PATCH 2/5] arm64: dts: apple: t8140: Group cache-related properties of cpus

[Yureka Lilian]

The dt-check-style from 7.3 raised an issue on the ordering, but
the one from current linux-next allows the cache properties to be
grouped, improving readability.

Signed-off-by: Yureka Lilian <yureka at cyberchaos.dev>
---
 arch/arm64/boot/dts/apple/t8140.dtsi | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/arch/arm64/boot/dts/apple/t8140.dtsi b/arch/arm64/boot/dts/apple/t8140.dtsi
index 150d91bdf6fc..40559da62923 100644
--- a/arch/arm64/boot/dts/apple/t8140.dtsi
+++ b/arch/arm64/boot/dts/apple/t8140.dtsi
@@ -60,8 +60,9 @@ cpu_e0: cpu at 0 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x0>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -71,8 +72,9 @@ cpu_e1: cpu at 1 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x1>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -82,8 +84,9 @@ cpu_e2: cpu at 2 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x2>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -93,8 +96,9 @@ cpu_e3: cpu at 3 {
 			compatible = "apple,tahiti-e";
 			reg = <0x0 0x3>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x10000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x10000>;
 			i-cache-size = <0x20000>;
 			next-level-cache = <&l2_cache_0>;
 		};
@@ -104,8 +108,9 @@ cpu_p0: cpu at 10100 {
 			compatible = "apple,tahiti-p";
 			reg = <0x0 0x10100>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x20000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x20000>;
 			i-cache-size = <0x30000>;
 			next-level-cache = <&l2_cache_1>;
 		};
@@ -115,8 +120,9 @@ cpu_p1: cpu at 10101 {
 			compatible = "apple,tahiti-p";
 			reg = <0x0 0x10101>;
 			cpu-release-addr = <0 0>;
-			d-cache-size = <0x20000>;
 			enable-method = "spin-table";
+
+			d-cache-size = <0x20000>;
 			i-cache-size = <0x30000>;
 			next-level-cache = <&l2_cache_1>;
 		};

-- 
2.55.0