[PATCH 0/3] clk: nuvoton: ma35d1: fix parent lookup and use the generic ADC divider

[Joey Lu]

The parent tables of the MA35D1 clock controller were converted to
struct clk_parent_data with only .fw_name set, but the controller node
has no clock-names, so the firmware lookup can never succeed and the clk
core only falls back to a global name lookup when .name is set. As a
result sysclk1_mux and everything below it (hclk*, pclk*, and the
peripheral dividers and gates) are orphans with a rate of 0 Hz, and
clk_set_rate() on their consumers returns early without programming the
hardware. This was found while testing the ADC clock, whose divider
register was never written.

Patch 1 fixes the parent lookup. Patches 2 and 3 replace the dedicated
ADC divider driver with the generic clk divider, as suggested in review
of the earlier "use direct formula instead of divider table" series,
which is dropped in favour of this one.

The earlier series:
https://lore.kernel.org/r/20261008064307.2757324-1-a0987203069@gmail.com

Joey Lu (3):
  clk: nuvoton: ma35d1: fix parent lookup for clk_parent_data entries
  clk: nuvoton: ma35d1: use the generic divider for the ADC clock
  clk: nuvoton: ma35d1: remove the unused ADC divider driver

 drivers/clk/nuvoton/Makefile             |   1 -
 drivers/clk/nuvoton/clk-ma35d1-divider.c | 133 -----------
 drivers/clk/nuvoton/clk-ma35d1.c         | 269 ++++++++++++-----------
 drivers/clk/nuvoton/clk-ma35d1.h         |   5 -
 4 files changed, 135 insertions(+), 273 deletions(-)
 delete mode 100644 drivers/clk/nuvoton/clk-ma35d1-divider.c

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2.43.0