[PATCH RFC v3 05/12] net: pcs: Add NXP S32G XPCS driver

[Jan Petrous]

On Sun, Sep 20, 2026 at 07:07:23PM +0200, Andrew Lunn wrote:
> > +#define SR_MII_CTRL				0x1f0000
> 
> This is 0x1f0000 + MII_BMCR
> 
> > +#define   SS13					BIT(13)
> 
> #define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
> 
> > +#define   AN_ENABLE				BIT(12)
> 
> #define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
> 
> > +#define   RESTART_AN				BIT(9)
> 
> #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
> 
> > +#define   DUPLEX_MODE				BIT(8)
> 
> #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
> 
> > +#define   SS6					BIT(6)
> 
> #define BMCR_SPEED1000          0x0040  /* MSB of Speed (1000)         */
> 
> > +#define SR_MII_STS				0x1f0001
> 
> This is 0x1f0000 + MII_BMSR
> 
> > +#define   LINK_STS				BIT(2)
> 
> #define BMSR_LSTATUS            0x0004  /* Link status                 */
> 
> Please go through all these register definitions and throw out all the
> ones which follow 801.3 and use the values from include/uapi/linux/mii.h
> 
>     Andrew
> 

Done for the next version. SR_MII_CTRL and SR_MII_STS and their bit
definitions are gone; the driver uses MII_BMCR, MII_BMSR and the BMCR_*
and BMSR_* bits from mii.h, addressed in MDIO_MMD_VEND2 rather than
through the flat 0x1fxxxx offsets.

Most of that code goes away anyway: with the move to pcs-xpcs (see the
patch 4 thread), the SGMII configuration and link state handling are
done by pcs-xpcs, which already uses mii.h. What stays in the S32G
driver is the PMA/PLL bring-up, and the definitions left there are the
Synopsys vendor registers at 0x8000 and above in MMD 31, which have no
mii.h equivalent. VR_MII_DIG_CTRL1, the one of them pcs-xpcs already
defines, is taken from pcs-xpcs.h.

Thanks,
Jan