[PATCH v2 00/23] arm64: Implement parallel CPU onlining with PSCI v0.2+

[Michael Kelley]

From: Will Deacon <will at kernel.org> Sent: Friday, October 9, 2026 3:07 AM
> 
> Hi everyone,
> 
> This is version two of the patches I previously posted here:
> 
>   https://lore.kernel.org/all/20260907164024.17164-1-will@kernel.org/
> 
> There have been quite a few changes since last time, thanks to all the
> feedback from humans and robots alike. These include:
> 
>   * Added tags (but I didn't carry over Pankaj's T-b, since the series
>     has changed a fair bit).
> 
>   * Fix secondary entry assembly code to handle timeouts correctly.
> 
>   * Fix stashing of MPIDR so that we don't clobber STACK_END_MAGIC.
> 
>   * Fix NULL dereference if PSCI fails to initialise.
> 
>   * Enable RCU as soon as a secondary CPU is alive.
> 
>   * Drop pointless (unreachable) optimisation to
>     arch_cpuhp_sync_state_poll().
> 
>   * Include cpufeature patches from Fuad so that 'cpu_data' is populated
>     with register values taking into account any cmdline overrides. This
>     is necessary for correct handling of 'boot_cpu_data' later on, where
>     the previous version of this series stashed a stale copy of mpamidr.
> 
> As before, the first four patches are small changes to the generic code
> to make it a little more "Arm-shaped" but the rest of the series is
> largely confined to the arm64 architecture and PSCI driver code.
> 
> The series is based on -rc2, as it otherwise conflicts with Fuad's GMID
> fix that was recently merged upstream.
> 

As I reported [1] for Jinjie Ruan's original series, I tested this series on an
ARM64 VM running on Hyper-V in the Azure cloud. Tested with 16 vCPUs
in the VM and with 96 vCPUs in the VM. No issues. I mainly wanted to
make sure nothing got crosswise with Hyper-V's implementation of PSCI.

Tested-by: Michael Kelley <mhklinux at outlook.com>

[1] https://lore.kernel.org/linux-arm-kernel/SN6PR02MB41575CD5883C01FCB7F35E2DD4182@SN6PR02MB4157.namprd02.prod.outlook.com/

> Cheers,
> 
> Will
> 
> Cc: Thomas Gleixner <tglx at kernel.org>
> Cc: Ben Horgan <ben.horgan at arm.com>
> Cc: Ștefania Ion <stefion at google.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Pankaj Patil <pankaj.patil at oss.qualcomm.com>
> Cc: Borislav Petkov <bp at alien8.de>
> Cc: Lorenzo Pieralisi <lpieralisi at kernel.org>
> Cc: Jinjie Ruan <ruanjinjie at huawei.com>
> Cc: Mark Rutland <mark.rutland at arm.com>
> Cc: Tarun Sahu <tarunsahu at google.com>
> Cc: Fuad Tabba <fuad.tabba at linux.dev>
> Cc: David Woodhouse <dwmw at amazon.co.uk>
> Cc: Peter Zijlstra <peterz at infradead.org>
> Cc: Marc Zyngier <maz at kernel.org>
> 
> --->8
> 
> Fuad Tabba (4):
>   arm64: cpufeature: Check arm64_ftr_regs[] before the first store
>   arm64: cpufeature: Add read_cpuid_with_overrides()
>   arm64: cpufeature: Read MPAMIDR_EL1 in __cpuinfo_store_cpu()
>   arm64: cpufeature: Store every ID register with its overrides applied
> 
> Will Deacon (19):
>   cpu/hotplug: Clean up cmpxchg() logic in cpuhp_can_boot_ap()
>   cpu/hotplug: Avoid trying to bring up CPUs that are already online
>   cpu/hotplug: Avoid busy-polling on archs where cpu_relax() is a no-op
>   cpu/hotplug: Propagate bring-up status to
>     arch_cpuhp_cleanup_kick_cpu()
>   arm64: smp: Tidy up smp_prepare_cpus()
>   arm64: smp: Tidy up cpuinfo init and cpufeature updates
>   arm64: smp: Defer update of secondary CPU capabilities
>   arm64: smp: Don't bother printing the I-cache policy for each CPU
>   arm64: smp: Defer RCU registration during secondary CPU bringup
>   arm64: smp: Use generic HOTPLUG_CORE_SYNC_FULL machinery for CPU
>     onlining
>   arm64: smp: Use generic HOTPLUG_SPLIT_STARTUP machinery for CPU
>     onlining
>   arm64: cpu_ops: Make 'cpu_operations' pointer global instead of
>     per-cpu
>   arm64: cpu_ops: Introduce get_secondary_cpu_ops()
>   firmware/psci: Cache PSCI v0.2+ version number to avoid redundant SMCs
>   firmware/psci: Extend ->cpu_on() callback to take an additional
>     argument
>   arm64: cpu_ops: Expose optional argument to target cpu in ->cpu_boot()
>   arm64: smp: Pass secondary CPU boot parameters via firmware if
>     possible
>   arm64: smp: Use generic HOTPLUG_PARALLEL machinery for CPU onlining
>   arm64: smp: Harden parallel CPU bringup against broken PSCI firmware
> 
>  arch/arm/kernel/psci_smp.c                |   4 +-
>  arch/arm64/Kconfig                        |   2 +-
>  arch/arm64/include/asm/cpu.h              |   7 +-
>  arch/arm64/include/asm/cpu_ops.h          |   7 +-
>  arch/arm64/include/asm/cpufeature.h       |  11 +
>  arch/arm64/include/asm/smp.h              |  40 ++-
>  arch/arm64/include/asm/topology.h         |   2 +
>  arch/arm64/kernel/acpi_parking_protocol.c |   3 +-
>  arch/arm64/kernel/asm-offsets.c           |   1 +
>  arch/arm64/kernel/cpu_ops.c               |  34 +-
>  arch/arm64/kernel/cpufeature.c            | 397 +++++++++++-----------
>  arch/arm64/kernel/cpuinfo.c               | 122 +++----
>  arch/arm64/kernel/head.S                  |  60 +++-
>  arch/arm64/kernel/psci.c                  |  14 +-
>  arch/arm64/kernel/smp.c                   | 183 +++++-----
>  arch/arm64/kernel/smp_spin_table.c        |   2 +-
>  arch/arm64/mm/mmu.c                       |   2 +-
>  arch/x86/kernel/smpboot.c                 |   4 +-
>  drivers/firmware/psci/psci.c              |  27 +-
>  include/linux/cpuhotplug.h                |   2 +-
>  include/linux/psci.h                      |   3 +-
>  include/linux/rcutree.h                   |   2 +-
>  kernel/cpu.c                              |  18 +-
>  23 files changed, 508 insertions(+), 439 deletions(-)
> 
> --
> 2.56.0.385.gd3acb90ef8-goog
>