[PATCH v9 0/2] Organize the SMMUv3 invalidation flow so iommupt can use it

[Jason Gunthorpe]

This is the last two patches Will didn't pick up from this series

See the original cover letter at:

 https://patch.msgid.link/r/0-v8-1eaaed5e0433+3d3d2d-smmu_tlbi_jgg@nvidia.com

v9:
 - Rename arm_smmu_compute_ttl() to arm_smmu_compute_range_ttl() for
   clarity
 - Fix the arm_smmu_tlb_inv_walk() to compute
      tlbi.table_levels_bitmap = GENMASK(level, 1);
   To be clear what the call contract is
 - No functional change, rebase on latest smmu/updates
v8: https://patch.msgid.link/r/0-v8-1eaaed5e0433+3d3d2d-smmu_tlbi_jgg@nvidia.com
 - Revise some comments/commit messages
 - Rebase onto smmu/updates and resolve a conflict
v7: https://patch.msgid.link/r/0-v7-e84261bbe7cd+2ea80b-smmu_tlbi_jgg@nvidia.com
 - Remove "RIL" in favor of "range inv" or "range invalidate"
 - No functional change, only renames, reflows, etc.
v6: https://patch.msgid.link/r/0-v6-9cd17417d355+281836-smmu_tlbi_jgg@nvidia.com
 - Rebase to v7.3-rc3
 - Add helpers arm_smmu_pt_level_to_lg2sz(), arm_smmu_pt_lg2sz_to_level(),
   arm_smmu_range_inv_calc_scale(), arm_smmu_range_inv_calc_num()
 - Remove unused leaf_only
 - Combine has_range_inv and range_inv_scale_max
 - Clarify comment on arm_smmu_iotlb_sync()
v5: https://patch.msgid.link/r/0-v5-b810cf379bfc+13d738-smmu_tlbi_jgg@nvidia.com
 - Rebase to v7.3-rc1
 - Fix the SVA CONT errata interaction
 - Remove over invalidation, instead use two overlapping range invalidations
 - Reflow patches around the errata work around
 - Fix a race when eliding INV_TYPE_S2_VMID_S1_CLEAR
v4: https://patch.msgid.link/r/0-v4-1802653d8886+492-smmu_tlbi_jgg@nvidia.com
 - Rebase on latest smmu branch (accomodate already merged IDR5_DS changes)
 - Fix iopte_size typo in interior patches
 - Tidy arm_smmu_ttl_addr_align() some more
v3: https://patch.msgid.link/r/0-v3-4e7f64f4e094+85e-smmu_tlbi_jgg@nvidia.com
 - Carry the base translation granule in the TLBI description and pass the
   domain separately
 - Invalidate the leaves when doing a table invalidation too, corrects a
   missed invalidation but means we don't do anything about the duplicate
   invalidations.
 - Simplify the control flow in a few places
 - Clarify the TTL derivation and accomodate DS
v2: https://patch.msgid.link/r/0-v2-43074a57a53a+fb95-smmu_tlbi_jgg@nvidia.com
 - Rebase to v7.2-rc1
v1: https://lore.kernel.org/all/0-v1-5b1ac97a5403+6588f-smmu_tlbi_jgg@nvidia.com/

Jason Gunthorpe (2):
  iommu/arm-smmu-v3: Change how the tlbi describes the invalidation
  iommu/arm-smmu-v3: Support the DS expansion of range invalidation
    SCALE

 .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c   |  29 ++-
 .../iommu/arm/arm-smmu-v3/arm-smmu-v3-test.c  |   4 +-
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c   | 215 +++++++++++++-----
 drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h   |  30 ++-
 4 files changed, 210 insertions(+), 68 deletions(-)


base-commit: 2888520bdcbe0599cfc77b2fad8dc6c95505a3cb
-- 
2.43.0