[PATCH v1 03/10] KVM: arm64: nv: Don't loop on AT S12E{0,1}{R,W} with an invalid VTCR_EL2

[Kajetan Puchalski]

On Mon, Sep 28, 2026 at 04:25:00PM +0100, Fuad Tabba wrote:

(..)

>  	stride = wi->pgshift - 3;
>  	input_size = get_ia_size(wi);
> -	if (input_size > 48 || input_size < 25)
> -		return -EFAULT;
> -
> -	ret = check_base_s2_limits(vcpu, wi, level, input_size, stride);
> -	if (ret) {
> +	if (input_size > 48 || input_size < 25 ||
> +	    check_base_s2_limits(vcpu, wi, level, input_size, stride)) {
>  		out->esr = compute_fsc(0, ESR_ELx_FSC_FAULT);
> -		return ret;
> +		return 1;
>  	}

While at it, we could also add a check to validate that the ipa being translated actually conforms
to the configuration. As per the Arm ARM (R_DRRZZ):

> When all of the following apply, the stage 2 translation IPA size check generates a stage 2 level 0 Translation fault:
> • Stage 2 translation is enabled.
> • The input address to stage 2 translation, whether or not stage 1 translation is enabled, is larger than the IA size
> configured in VTCR_EL2.T0SZ or VSTCR_EL2.T0SZ, as appropriate for the IPA space.

Currently we just clear out the upper bits of an address larger than the IA size and proceed, but
the architecture requires that to cause a L0 translation fault. Not that it's a particularly common case.
That is to say, I'm suggesting something like the following:

+ if (input_size > 48 || input_size < 25 || (ipa >> input_size) ||
+    check_base_s2_limits(vcpu, wi, level, input_size, stride)) {