[PATCH] arm64: dts: rockchip: add pcie30phy data-lanes on rk3588 coolpi-cm5-evb

[Shawn Lin]

Both pcie3x2 (PHY port1) and pcie3x4 (PHY port0) are enabled, but
pcie30phy had no data-lanes. Without it the PHY defaults to aggregation
mode and assigns all four lanes to port0, leaving pcie3x2 without lanes
and unable to establish a link. Set data-lanes = <1 1 2 2> to split the
lanes as 2+2 between the two controllers.

Signed-off-by: Shawn Lin <shawn.lin at rock-chips.com>
---

 arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts
index 66e3c20..c269fdb 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-coolpi-cm5-evb.dts
@@ -198,6 +198,7 @@
 };
 
 &pcie30phy {
+	data-lanes = <1 1 2 2>;
 	status = "okay";
 };
 
-- 
2.7.4