[PATCH v2 0/6] dmaengine: arm-dma350: Add slave support and CIX Sky1 integration

Jelly Jia Jelly.Jia at cixtech.com
Thu Oct 8 22:18:40 PDT 2026


Hello,

This series adds slave transfer support to the Arm DMA-350 driver and
the CIX Sky1 SoC integration around it.

Patch 1 fixes the CH_CTRL_USESRCTRIGIN definition: the source trigger
enable bit is bit 25, not bit 26 (which is the destination trigger
enable bit). Unchanged since v1.

Patch 2 adds slave transfer support to the Arm DMA-350 driver:
scatter-gather and cyclic preparation, command-list allocation,
per-channel resource mapping and residue reporting. Slave transfers are
needed to serve peripheral requests, for example the audio FIFOs of the
CIX Sky1 audio subsystem.

Patch 3 is new in v2: it syncs the slave command list before starting a
transfer. The command list is mapped with dma_map_single(), so without
the sync a non-coherent DMA-350 may read stale command words and the
transfer stalls after the first command.

Patch 4 documents the CIX Sky1 DMA-350 integration in the arm,dma-350
binding: the Sky1 controller keeps the generic compatible and adds a
"cix,sky1-dma350" device compatible, with clocks, resets, interrupt
routing through a syscon phandle and an optional reserved memory pool
described on the controller node.

Patch 5 adds the matching driver support, which manages those resources;
slave resources are mapped with dma_map_resource() and translated by the
DMA API through the parent bus dma-ranges.

Patch 6 adds the two Sky1 instances (FCH and AUDSS) to the SoC
devicetree, each under a simple-bus node describing the bus integration.

Changes since v1:
- The wrapper node is gone. The Sky1 DMA-350 is described by a single
  device node with "cix,sky1-dma350", "arm,dma-350" and its real MMIO
  region, carrying the clock, reset and interrupt routing that v1 kept
  on the wrapper; the separate cix,sky1-dma350 binding and the wrapper
  driver are dropped. The integration and the block are one device, and
  the MMIO is unchanged. Thanks to Krzysztof Kozlowski and Conor Dooley
  for the review.
- The FCH and AUDSS DMA-350 masters sit behind SoC interconnect windows
  in a static DMA address domain, so their DMA view differs from the CPU
  physical view; the windows are fixed before Linux boots, so Linux
  cannot manage them as an interconnect. They are described with a
  generic "simple-bus" address-domain parent carrying the window
  "dma-ranges", not with a CIX DMA wrapper device: the parent has no
  device-specific or vendor wrapper compatible, only the generic
  "simple-bus" compatible, and no reg, clocks, resets or driver of its
  own. The OF DMA core builds dev->dma_range_map from that parent
  property and the DMA API applies it; the driver has no private
  translation. Same shape as the mainline Agilex5 and Marvell AC5 buses;
  patch 6 explains the hardware in detail.
- Patch 2 now allocates the command list with kmalloc()/dma_map_single()
  instead of dma_alloc_coherent(), because it is freed from the virt-dma
  tasklet where dma_free_coherent() may not be called; it picks a free
  trigger-capable channel in .of_xlate(); and it reads the link address
  registers in a retry loop, since the channel can step the link pointer
  between the two reads.
- Patch 3 is new, see above.
- Patch 5 merged the Sky1 integration into arm-dma350.c; slave resources
  are mapped with dma_map_resource() and translated by the DMA API
  through the parent bus dma-ranges.

The series is based on v7.3-rc1.

Testing:
- Built for arm64 with GCC 12.3, no new warnings; sparse clean;
  checkpatch --strict clean.
- dt_binding_check and dtbs_check pass for the new binding and nodes.
- Runtime-tested on a CIX Sky1 (Radxa Orion O6) board: both the FCH and
  the AUDSS DMA-350 instances probe and transfer data, and audio
  playback through the AUDSS DMA-350 runs without underruns.

Assisted-by: LLM checkpatch sparse dt_binding_check dtbs_check
Signed-off-by: Jelly Jia <Jelly.Jia at cixtech.com>

Jelly Jia (6):
  dmaengine: arm-dma350: Fix source trigger bit
  dmaengine: arm-dma350: Add slave and cyclic transfer support
  dmaengine: arm-dma350: Sync the slave command list before starting
  dt-bindings: dma: arm,dma-350: Document the CIX Sky1 integration
  dmaengine: arm-dma350: Add CIX Sky1 integration support
  arm64: dts: cix: Describe the Sky1 DMA-350 bus integration

 .../devicetree/bindings/dma/arm,dma-350.yaml  |  33 +-
 arch/arm64/boot/dts/cix/sky1.dtsi             |  66 +-
 drivers/dma/Kconfig                           |   4 +
 drivers/dma/arm-dma350.c                      | 717 +++++++++++++++++-
 4 files changed, 783 insertions(+), 37 deletions(-)


base-commit: cee9395acd8043be0644b25c34bfa86623f2b935
-- 
2.54.0




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