[PATCH 0/3] pinctrl: s32cc: add GPIO external interrupt (EIRQ) support

[Khristine Andreea Barbulescu]

This patch series adds support for using SIUL2 GPIOs as external
interrupts (EIRQ) via the pin controller's IRQ domain.

A GPIO wired to an EIRQ line can be used as an edge-triggered interrupt
source. All EIRQ lines share a single parent interrupt, which is
demultiplexed to the owning GPIO in a chained handler.

Each EIRQ line is selected by one pad through the IMCR input-mux SSS
field. Since several pads share the same SSS field, only one pad can
drive a given EIRQ line at a time, so the driver enforces one owner per
EIRQ line.

This series builds on top of the SIUL2 GPIO support
and has two dependencies:

- GPIO commit 94cb9e8f2707 ("pinctrl: s32cc: implement GPIO functionality")
which is pending a rebase to be applied on the GPIO tree, as referenced
in the following commit 04b3818c3bbc
("Revert "pinctrl: s32cc: implement GPIO functionality"") [1]

- align reg_mask_xlate callback with commit 6c53312b7e2d
("gpio: regmap: Add gpio_regmap_operation to extend reg_mask_xlate callback")

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=04b3818c3bbc3f68b6e856f87dca752af2cc34ee

Khristine Andreea Barbulescu (3):
  dt-bindings: pinctrl: s32g2-siul2: describe EIRQ input mux registers
  pinctrl: s32cc: add GPIO external interrupt (EIRQ) support
  arm64: dts: s32g: map SIUL2 EIRQ register window in pinctrl node

 .../pinctrl/nxp,s32g2-siul2-pinctrl.yaml      |   9 +-
 arch/arm64/boot/dts/freescale/s32g2.dtsi      |   2 +
 arch/arm64/boot/dts/freescale/s32g3.dtsi      |   2 +
 drivers/pinctrl/nxp/pinctrl-s32.h             |  32 ++
 drivers/pinctrl/nxp/pinctrl-s32cc.c           | 406 ++++++++++++++++++
 drivers/pinctrl/nxp/pinctrl-s32g2.c           |  72 ++++
 6 files changed, 521 insertions(+), 2 deletions(-)

-- 
2.34.1