[PATCH v4 06/15] iio: adc: xilinx-xadc: Use guard()/scoped_guard() for spinlock locking
Dileep Kumar Nagavarapu
dileepkumar.nagavarapu at amd.com
Mon Oct 5 02:41:56 PDT 2026
Use guard() and scoped_guard() helpers for spinlock handling
instead of spin_lock/spin_unlock sequences.
This removes the need for explicit spin_unlock()
No functional change intended.
Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri at amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri at amd.com>
Signed-off-by: Dileep Kumar Nagavarapu <dileepkumar.nagavarapu at amd.com>
---
drivers/iio/adc/xilinx-xadc-core.c | 97 ++++++++++++++----------------
1 file changed, 45 insertions(+), 52 deletions(-)
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index 9e4955016bbc..0234c8301c2e 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -13,6 +13,7 @@
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/device.h>
#include <linux/err.h>
@@ -155,19 +156,19 @@ static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg, u16 val)
u32 tmp;
int ret;
- spin_lock_irq(&xadc->lock);
- xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
+ scoped_guard(spinlock_irq, &xadc->lock) {
+ xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
- reinit_completion(&xadc->completion);
+ reinit_completion(&xadc->completion);
- cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
- xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
- xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
- tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
- xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
+ cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
+ xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
+ xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
+ tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
+ xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
- xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
- spin_unlock_irq(&xadc->lock);
+ xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
+ }
ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
if (ret == 0)
@@ -189,19 +190,20 @@ static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg, u16 *val)
cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
- spin_lock_irq(&xadc->lock);
- xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
- xadc_zynq_drain_fifo(xadc);
- reinit_completion(&xadc->completion);
+ scoped_guard(spinlock_irq, &xadc->lock) {
+ xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, XADC_ZYNQ_INT_DFIFO_GTH);
+ xadc_zynq_drain_fifo(xadc);
+ reinit_completion(&xadc->completion);
- xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
- xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
- tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
- tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1);
- xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
+ xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
+ xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
+ tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
+ tmp |= FIELD_PREP(XADC_ZYNQ_CFG_DFIFOTH_MASK, 1);
+ xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
+
+ xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
+ }
- xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
- spin_unlock_irq(&xadc->lock);
ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
if (ret == 0)
ret = -EIO;
@@ -238,21 +240,19 @@ static void xadc_zynq_unmask_worker(struct work_struct *work)
misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
- spin_lock_irq(&xadc->lock);
+ scoped_guard(spinlock_irq, &xadc->lock) {
+ /* Clear those bits which are not active anymore */
+ unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
+ xadc->zynq_masked_alarm &= misc_sts;
- /* Clear those bits which are not active anymore */
- unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
- xadc->zynq_masked_alarm &= misc_sts;
+ /* Also clear those which are masked out anyway */
+ xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
- /* Also clear those which are masked out anyway */
- xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
+ /* Clear the interrupts before we unmask them */
+ xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
- /* Clear the interrupts before we unmask them */
- xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
-
- xadc_zynq_update_intmsk(xadc, 0, 0);
-
- spin_unlock_irq(&xadc->lock);
+ xadc_zynq_update_intmsk(xadc, 0, 0);
+ }
/* if still pending some alarm re-trigger the timer */
if (xadc->zynq_masked_alarm) {
@@ -274,7 +274,7 @@ static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
if (!status)
return IRQ_NONE;
- spin_lock(&xadc->lock);
+ guard(spinlock)(&xadc->lock);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
@@ -298,7 +298,6 @@ static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
schedule_delayed_work(&xadc->zynq_unmask_work,
msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
}
- spin_unlock(&xadc->lock);
return IRQ_HANDLED;
}
@@ -393,21 +392,18 @@ static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
{
- unsigned long flags;
u32 status;
/* Move OT to bit 7 */
alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
- spin_lock_irqsave(&xadc->lock, flags);
+ guard(spinlock_irqsave)(&xadc->lock);
/* Clear previous interrupts if any. */
xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK, ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
-
- spin_unlock_irqrestore(&xadc->lock, flags);
}
static const struct xadc_ops xadc_zynq_ops = {
@@ -492,7 +488,6 @@ static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
{
- unsigned long flags;
u32 val;
/*
@@ -503,12 +498,11 @@ static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
*/
alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) | ((alarm & 0xf0) << 6);
- spin_lock_irqsave(&xadc->lock, flags);
+ guard(spinlock_irqsave)(&xadc->lock);
xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
val &= ~XADC_AXI_INT_ALARM_MASK;
val |= alarm;
xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
- spin_unlock_irqrestore(&xadc->lock, flags);
}
static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
@@ -651,7 +645,6 @@ static irqreturn_t xadc_trigger_handler(int irq, void *p)
static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
{
struct xadc *xadc = iio_trigger_get_drvdata(trigger);
- unsigned long flags;
unsigned int convst;
unsigned int val;
int ret = 0;
@@ -677,15 +670,15 @@ static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
xadc->trigger = NULL;
}
- spin_lock_irqsave(&xadc->lock, flags);
- xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
- xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
- if (state)
- val |= XADC_AXI_INT_EOS;
- else
- val &= ~XADC_AXI_INT_EOS;
- xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
- spin_unlock_irqrestore(&xadc->lock, flags);
+ scoped_guard(spinlock_irqsave, &xadc->lock) {
+ xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
+ xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
+ if (state)
+ val |= XADC_AXI_INT_EOS;
+ else
+ val &= ~XADC_AXI_INT_EOS;
+ xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
+ }
err_out:
mutex_unlock(&xadc->mutex);
--
2.34.1
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