[PATCH v4] arm64: errata: Add NXP iMX8QM workaround for A53 cache coherency issue

[Francesco Dolcini]

Hello,

On Tue, Sep 15, 2026 at 11:02:54PM +0800, Peng Fan wrote:
> On Mon, Aug 24, 2026 at 12:02:04PM +0800, Peng Fan (OSS) wrote:
> >From: Peng Fan <peng.fan at nxp.com>
> >
> >According to NXP errata document IMX8_1N94W[1], the i.MX8QuadMax SoC
> >suffers from a cache coherency issue (ERR050104). The upper bits, above
> >bit 35, of the ARADDR and ACADDR buses within the Arm A53 subsystem
> >have been incorrectly connected. This causes some TLBI and IC
> >maintenance operations exchanged between the A53 and A72 core clusters
> >to be corrupted.
> >
> 
> Any comments?

Any plan to have this merged?

Francesco