[PATCH v2 1/3] spi: dt-bindings: nuvoton,ma35d1-qspi: Add MA35D1 SPI controller

[Krzysztof Kozlowski]

On Thu, Oct 01, 2026 at 09:18:16PM +0800, Chi-Wen Weng wrote:
> From: Chi-Wen Weng <cwweng at nuvoton.com>
> 
> Extend the existing MA35D1 QSPI binding to also describe the MA35D1 SPI
> controller.
> 
> The SPI and QSPI controllers are separate hardware IPs. QSPI additionally
> supports dual, quad and DTR transfers and a target-mode timeout function,
> but these differences do not require additional controller-specific
> Devicetree properties.
> 
> Both controllers expose the same Devicetree-visible resources and provide
> up to two native chip-select signals. GPIO chip selects are supported
> through the generic SPI controller binding. Since the MA35D1 QSPI driver
> now supports GPIO chip selects, also remove the existing restriction
> on cs-gpios for the QSPI compatible.

This has to be a separate commit.

> 
> Add the nuvoton,ma35d1-spi compatible and update the binding description
> and examples to cover both controllers.
> 
> Signed-off-by: Chi-Wen Weng <cwweng at nuvoton.com>
> ---
>  .../bindings/spi/nuvoton,ma35d1-qspi.yaml     | 41 +++++++++++++++++--
>  1 file changed, 37 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> index 40965ec5163b..72f2e1e1219a 100644
> --- a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml
> @@ -4,7 +4,17 @@
>  $id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml#
>  $schema: http://devicetree.org/meta-schemas/core.yaml#
>  
> -title: Nuvoton MA35D1 Quad SPI Controller
> +title: Nuvoton MA35D1 SPI and Quad SPI Controllers
> +
> +description: |
> +  The Nuvoton MA35D1 SoC contains separate SPI and QSPI controller IPs.
> +  Both controllers expose the same Devicetree-visible resources and provide
> +  two native chip-select signals. GPIO chip selects are supported through the
> +  generic SPI controller binding.
> +
> +  The QSPI controller additionally supports dual, quad and DTR transfers and
> +  a target-mode timeout function. These capability differences do not require
> +  additional controller properties.
>  
>  maintainers:
>    - Chi-Wen Weng <cwweng at nuvoton.com>
> @@ -14,7 +24,9 @@ allOf:
>  
>  properties:
>    compatible:
> -    const: nuvoton,ma35d1-qspi
> +    enum:
> +      - nuvoton,ma35d1-spi
> +      - nuvoton,ma35d1-qspi
>  
>    reg:
>      maxItems: 1
> @@ -33,8 +45,6 @@ properties:
>      maximum: 2
>      default: 2
>  
> -  cs-gpios: false
> -
>  required:
>    - compatible
>    - reg
> @@ -59,7 +69,30 @@ examples:
>              interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
>              clocks = <&clk QSPI0_GATE>;
>              resets = <&sys MA35D1_RESET_QSPI0>;
> +
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +        };
> +    };
> +
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> +    #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
> +

No need for a new example, for exactly the same node. Difference in
value of a property does not justify it.

Best regards,
Krzysztof