[PATCH v21 14/15] tools: Synchronise the kernel esr.h

[Lorenzo Stoakes (ARM)]

On Wed, Sep 30, 2026 at 10:48:24PM +0100, Mark Brown wrote:
> To pick up definitions for GCS.
>
> Reviewed-by: Leonardo Bras <leo.bras at arm.com>
> Signed-off-by: Mark Brown <broonie at kernel.org>

This seems to be out of date, with your series applied to next:

$ diff -u arch/arm64/include/asm/esr.h tools/arch/arm64/include/asm/esr.h
--- arch/arm64/include/asm/esr.h	2026-10-01 17:43:56.186852562 +0100
+++ tools/arch/arm64/include/asm/esr.h	2026-10-01 17:43:56.194056154 +0100
@@ -7,7 +7,6 @@
 #ifndef __ASM_ESR_H
 #define __ASM_ESR_H

-#include <asm/memory.h>
 #include <asm/sysreg.h>

 #define ESR_ELx_EC_UNKNOWN	UL(0x00)
@@ -131,7 +130,7 @@
  * Annoyingly, the negative levels for Address size faults aren't laid out
  * contiguously (or in the desired order)
  */
-#define ESR_ELx_FSC_ADDRSZ_nL(n)	((n) == -1 ? 0x29 : 0x2C)
+#define ESR_ELx_FSC_ADDRSZ_nL(n)	((n) == -1 ? 0x25 : 0x2C)
 #define ESR_ELx_FSC_ADDRSZ_L(n)		((n) < 0 ? ESR_ELx_FSC_ADDRSZ_nL(n) : \
 						   (ESR_ELx_FSC_ADDRSZ + (n)))

@@ -437,35 +436,6 @@
 #ifndef __ASSEMBLER__
 #include <asm/types.h>

-static __always_inline bool esr_trap_is_iabt(unsigned long esr)
-{
-	return ESR_ELx_EC(esr) == ESR_ELx_EC_IABT_LOW;
-}
-
-/* Always check for S1PTW *before* using this. */
-static __always_inline bool esr_dabt_is_write(unsigned long esr)
-{
-	return esr & ESR_ELx_WNR;
-}
-
-static __always_inline bool esr_dabt_is_cm(unsigned long esr)
-{
-	return esr & ESR_ELx_CM;
-}
-
-static __always_inline bool esr_abt_is_sea(unsigned long esr)
-{
-	switch (esr & ESR_ELx_FSC) {
-	case ESR_ELx_FSC_EXTABT:
-	case ESR_ELx_FSC_SEA_TTW(-1) ... ESR_ELx_FSC_SEA_TTW(3):
-	case ESR_ELx_FSC_SECC:
-	case ESR_ELx_FSC_SECC_TTW(-1) ... ESR_ELx_FSC_SECC_TTW(3):
-		return true;
-	default:
-		return false;
-	}
-}
-
 static inline unsigned long esr_brk_comment(unsigned long esr)
 {
 	return esr & ESR_ELx_BRK64_ISS_COMMENT_MASK;

--
Cheers, Lorenzo