[PATCH 2/2] gpio: aspeed: Preserve the pending G7 interrupt status on control writes

[Andrew Jeffery]

On Wed, 2026-11-04 at 11:58 +0800, Billy Tsai wrote:
> On G7 each line has its own control register, and its interrupt status
> bit (bit 12) is write-1-to-clear. aspeed_g7_reg_bit_set() updates a
> field by reading the control register, replacing that field and writing
> the value back. When the line's interrupt is pending, the status bit
> reads as 1 and is written back as 1, so updating an unrelated field
> such as the interrupt enable, trigger type, direction or debounce
> selection also clears the pending interrupt.
> 
> Mask out the status bit when composing the value to write, so it is
> written as 1 only when the status field itself is being set to ack the
> interrupt.
> 
> Fixes: b2e861bd1eaf ("gpio: aspeed: Support G7 Aspeed gpio controller")
> Cc: stable at vger.kernel.org
> Signed-off-by: Billy Tsai <billy_tsai at aspeedtech.com>

Reviewed-by: Andrew Jeffery <andrew at codeconstruct.com.au>