[PATCH v3 1/3] dt-bindings: arm: cpus: Add brcm,bca-smp enable method

[William Zhang]

On Tue, Nov 3, 2026 at 1:38 PM Rob Herring <robh at kernel.org> wrote:
>
> On Fri, Oct 23, 2026 at 09:20:06PM -0700, William Zhang wrote:
> > On Thu, Oct 22, 2026 at 7:15 AM Rob Herring <robh at kernel.org> wrote:
> > >
> > > On Wed, Oct 21, 2026 at 05:09:52PM +0200, Linus Walleij wrote:
> > > > BCMBCA systems booted through CFE can release a secondary CPU by
> > > > writing its ARM-state entry address to a 32-bit MMIO mailbox and
> > > > sending a wakeup interrupt.
> > > >
> > > > Document brcm,bca-smp and its single-cell cpu-release-addr property.
> > > > The boot CPU does not need a mailbox; secondary CPUs do. Add a
> > > > Cortex-A7 example showing both CPU nodes.
> > > >
> > > > Suggested-by: William Zhang <william.zhang at broadcom.com>
> > > > Signed-off-by: Linus Walleij <linusw at kernel.org>
> > > > ---
> > > >  Documentation/devicetree/bindings/arm/cpus.yaml | 36 +++++++++++++++++++++++++
> > > >  1 file changed, 36 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
> > > > index 5be89c584026..6771b85f757b 100644
> > > > --- a/Documentation/devicetree/bindings/arm/cpus.yaml
> > > > +++ b/Documentation/devicetree/bindings/arm/cpus.yaml
> > > > @@ -255,6 +255,7 @@ properties:
> > > >            - amlogic,meson8b-smp
> > > >            - arm,realview-smp
> > > >            - aspeed,ast2600-smp
> > > > +          - brcm,bca-smp
> > > >            - brcm,bcm11351-cpu-method
> > > >            - brcm,bcm23550
> > > >            - brcm,bcm2836-smp
> > > > @@ -471,6 +472,20 @@ allOf:
> > > >      then:
> > > >        required:
> > > >          - secondary-boot-reg
> > > > +  - if:
> > > > +      properties:
> > > > +        enable-method:
> > > > +          const: brcm,bca-smp
> > > > +      required:
> > > > +        - enable-method
> > > > +    then:
> > > > +      properties:
> > > > +        cpu-release-addr:
> > > > +          $ref: /schemas/types.yaml#/definitions/uint32
> > > > +          description:
> > > > +            Physical address of the 32-bit MMIO mailbox read by CFE after
> > > > +            a wakeup interrupt. Required on secondary CPUs. The kernel
> > > > +            writes the ARM-state entry address before sending the interrupt.
> > >
> > > required:
> > >   - cpu-release-addr
> > >
> > > ??? But cpu0 doesn't have an address. Is there really no address or you
> > > just omitted because you don't really need it. Should still be there in
> > > the latter case IMO.
> > >
> > > Alternatively, add the enable-method value to the existing section that
> > > does this. Also, there might be other cases that are a 32-bit address
> > > and need this same constraint.
> > >
> > Cpu0 does not need release because it is the boot up CPU.
>
> I get that. Is that convention or h/w restriction? I seem to recall the
> arm32 kernel might require cpu0 booting, but I think other arches do
> not. What if you support power gating or hot unplug of CPU0? Then you'd
> need the address.
>
For hotplug,  I remember the address will be provided by kernel using
the kernel's cpu entry point,
not the same release address provided by the bootloader.

> >  But there
> > is no harm to add it to be consistent.
>
> If there is an release address for cpu0, then yes, you should have the
> property. If there is not and you just have to make up something to be
> consistent, then you should not have the property.
Then I think we should not add the release address for cpu0 as it is
not really applicable.

>
>
> Rob
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/pkcs7-signature
Size: 5473 bytes
Desc: S/MIME Cryptographic Signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20261104/0d66e0a3/attachment-0001.p7s>