[PATCH v7 05/12] serial: 8250_dw: derive RX trigger thresholds from the FIFO depth

[Andy Shevchenko]

On Tue, Nov 03, 2026 at 02:39:58PM -0700, James Hilliard wrote:
> DW_apb_uart uses receive thresholds of one byte, one quarter full,
> one half full and two bytes below full. The generic 16550A table describes
> these encodings only for a 16-byte FIFO. For example, the half-full setting
> on a 64-byte DW FIFO is reported as eight bytes instead of 32, and a sysfs
> request for 32 bytes selects the 62-byte encoding.
> 
> Build a per-port threshold table from the discovered FIFO depth in dwlib
> and install receive-trigger callbacks for CPR-described FIFOs, including
> LPSS ports. Keep the setup helper available to integrations which obtain
> the depth without probing the optional DW registers. Validate that each
> threshold is positive and representable before constructing the table.
> 
> Serialize FCR updates with termios and the port lock, acquire a runtime PM
> reference before accessing the device, and propagate resume errors without
> changing the shadow or hardware. Update only the trigger field so changing
> the threshold preserves the FIFO contents.
> 
> The FCR mapping is documented in the DW_apb_uart databook, section 6,
> FIFO Control Register. The existing default FCR encoding is unchanged.

...

>  static int dw8250_setup(struct uart_port *p)
>  {
> -	dw8250_setup_port(p);
> +	int ret;
> +
> +	ret = dw8250_setup_port(p);
> +	if (ret)
> +		return ret;
> +
>  	return dw8250_setup_dma(p);
>  }

Split out a change that moves from void to int for _setup_port() and do it
before the patch that creates _setup_dma(), so it will be less churn overall.

...

> struct dw8250_port_data {

>  	/* Hardware configuration */
>  	u32			cpr_value;
>  	u8			dlf_size;
> +	u16			rxtrig_bytes[UART_FCR_R_TRIG_MAX_STATE];

Put it first after the above comment. Check with `pahole` before and after
results.

>  	/* RS485 variables */
>  	bool			hw_rs485_support;

-- 
With Best Regards,
Andy Shevchenko