[PATCH 07/10] dt-bindings: ufs: Add NXP S32N79 UFS host controller

[Larisa Ileana Grigore]

On 10/26/2026 1:11 PM, Krzysztof Kozlowski wrote:
> On Sat, Oct 24, 2026 at 02:25:30PM +0200, Larisa Grigore wrote:
>> Document the UFS host controller on the NXP S32N79 SoC.
>>
>> Signed-off-by: Larisa Grigore <larisa.grigore at oss.nxp.com>
>> Reviewed-by: Frank Li <Frank.Li at nxp.com>
> 
> How this could appear in v1?
> 
> Also, your SoB is the last one.
> 

Apologies for the confusion. This was intended to be v9. I will send v10.

Regards,
Larisa
>> ---
>>   .../bindings/ufs/nxp,s32n79-ufshc.yaml        | 65 +++++++++++++++++++
>>   1 file changed, 65 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
>> new file mode 100644
>> index 000000000000..14291c5506f1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ufs/nxp,s32n79-ufshc.yaml
>> @@ -0,0 +1,65 @@
>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/ufs/nxp,s32n79-ufshc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: NXP S32N79 Universal Flash Storage (UFS) Controller
>> +
>> +maintainers:
>> +  - Larisa Grigore <larisa.grigore at oss.nxp.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: nxp,s32n79-ufshc
>> +
>> +  reg:
>> +    items:
>> +      - description: UFS Host Controller registers
>> +      - description: System Control Module registers
>> +
>> +  reg-names:
>> +    items:
>> +      - const: ufshc
>> +      - const: scm
>> +
>> +  clocks:
>> +    maxItems: 1
>> +
>> +  clock-names:
>> +    items:
>> +      - const: core
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - clocks
>> +  - clock-names
>> +  - operating-points-v2
>> +
>> +allOf:
>> +  - $ref: ufs-common.yaml
>> +
>> +unevaluatedProperties: false
>> +
>> +examples:
>> +  - |
>> +    ufshc at 4ac80000 {
>> +        compatible = "nxp,s32n79-ufshc";
>> +        reg = <0x4ac80000 0x1000>, <0x4ac40000 0x1000>;
>> +        reg-names = "ufshc", "scm";
>> +        interrupt-parent = <&irqsteer_coss>;
>> +        interrupts = <211>;
>> +        clocks = <&clks 0x92>;
>> +        clock-names = "core";
>> +        operating-points-v2 = <&ufs_opp_table>;
>> +
>> +        ufs_opp_table: opp-table {
>> +            compatible = "operating-points-v2";
>> +
>> +            opp-0 {
>> +                opp-hz = /bits/ 64 <0>;
> 
> Why is this empty?
> 
> 
> Best regards,
> Krzysztof
>