[PATCH 5/5] arm64: dts: lx2160a: describe the pad muxes as the DCFG RCW override
Vincent Jardin via B4 Relay
devnull+vjardin.free.fr at kernel.org
Tue Nov 3 01:51:58 PST 2026
From: Vincent Jardin <vjardin at free.fr>
The pad muxes are fields of the RCW: read-only in RCWSR12..14, changed
at runtime through the override registers in the DCSR view of DCFG,
which read 0 until written.
pinctrl-single on those registers, since commit 8a1365c7bbc1
("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery"),
clears every other field of the word with its first pin state:
a board whose RCW programs a non-zero pad mux loses those pads at the
first I2C probe.
Describe the pad mux as a child of the dcfg node, which gains its DCSR
view: one group per RCW field, one function per encoding, driven by
fsl,lx2160a-rcw-pinmux through fsl-guts. Labels and node names stay,
so no consumer changes. The pinctrl-single node goes.
Signed-off-by: Vincent Jardin <vjardin at free.fr>
---
arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi | 373 ++++++++++++++------------
1 file changed, 198 insertions(+), 175 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
index 2085362ab0ea..23e662d235a4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx216x.dtsi
@@ -669,9 +669,205 @@ clockgen: clock-controller at 1300000 {
};
dcfg: syscon at 1e00000 {
- compatible = "fsl,lx2160a-dcfg", "syscon";
- reg = <0x0 0x1e00000 0x0 0x10000>;
+ compatible = "fsl,lx2160a-dcfg", "syscon", "simple-mfd";
+ reg = <0x0 0x1e00000 0x0 0x10000>,
+ <0x7 0x00100000 0x0 0x10000>;
+ reg-names = "dcfg_ccsr", "dcfg_dcsr";
little-endian;
+
+ pinmux_i2crv: pinctrl {
+ compatible = "fsl,lx2160a-rcw-pinmux";
+
+ i2c1_pins: iic2-i2c-pins {
+ function = "i2c";
+ groups = "iic2";
+ };
+
+ gpio0_31_30_pins: iic2-gpio-pins {
+ function = "gpio";
+ groups = "iic2";
+ };
+
+ ftm0_ch10_pins: iic2-ftm-pins {
+ function = "flextimer";
+ groups = "iic2";
+ };
+
+ esdhc0_cd_wp_pins: iic2-sdhc-pins {
+ function = "sdhc";
+ groups = "iic2";
+ };
+
+ i2c2_pins: iic3-i2c-pins {
+ function = "i2c";
+ groups = "iic3";
+ };
+
+ gpio0_29_28_pins: iic3-gpio-pins {
+ function = "gpio";
+ groups = "iic3";
+ };
+
+ can0_pins: iic3-can-pins {
+ function = "can";
+ groups = "iic3";
+ };
+
+ event65_pins: iic3-event-pins {
+ function = "evt";
+ groups = "iic3";
+ };
+
+ i2c3_pins: iic4-i2c-pins {
+ function = "i2c";
+ groups = "iic4";
+ };
+
+ gpio0_27_26_pins: iic4-gpio-pins {
+ function = "gpio";
+ groups = "iic4";
+ };
+
+ can1_pins: iic4-can-pins {
+ function = "can";
+ groups = "iic4";
+ };
+
+ event87_pins: iic4-event-pins {
+ function = "evt";
+ groups = "iic4";
+ };
+
+ i2c4_pins: iic5-i2c-pins {
+ function = "i2c";
+ groups = "iic5";
+ };
+
+ gpio0_25_24_pins: iic5-gpio-pins {
+ function = "gpio";
+ groups = "iic5";
+ };
+
+ esdhc0_clksync_pins: iic5-sdhc-clk-pins {
+ function = "sdhc-clk";
+ groups = "iic5";
+ };
+
+ dspi2_miso_mosi_pins: iic5-spi3-pins {
+ function = "spi";
+ groups = "iic5";
+ };
+
+ i2c5_pins: iic6-i2c-pins {
+ function = "i2c";
+ groups = "iic6";
+ };
+
+ gpio0_23_22_pins: iic6-gpio-pins {
+ function = "gpio";
+ groups = "iic6";
+ };
+
+ esdhc1_clksync_pins: iic6-sdhc-clk-pins {
+ function = "sdhc-clk";
+ groups = "iic6";
+ };
+
+ fspi_data74_pins: xspi1-data74-pins {
+ function = "flexspi";
+ groups = "xspi1-data74";
+ };
+
+ gpio1_31_28_pins: xspi1-data74-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-data74";
+ };
+
+ fspi_data30_pins: xspi1-data30-pins {
+ function = "flexspi";
+ groups = "xspi1-data30";
+ };
+
+ gpio1_27_24_pins: xspi1-data30-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-data30";
+ };
+
+ fspi_dqs_sck_cs10_pins: xspi1-base-pins {
+ function = "flexspi";
+ groups = "xspi1-base";
+ };
+
+ gpio1_23_20_pins: xspi1-base-gpio-pins {
+ function = "gpio";
+ groups = "xspi1-base";
+ };
+
+ esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
+ function = "sdhc";
+ groups = "sdhc1-base";
+ };
+
+ gpio0_21_15_pins: sdhc1-base-gpio-pins {
+ function = "gpio";
+ groups = "sdhc1-base";
+ };
+
+ dspi0_pins: sdhc1-base-spi1-pins {
+ function = "spi";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
+ function = "sdhc-spi";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
+ function = "sdhc-data4";
+ groups = "sdhc1-base";
+ };
+
+ esdhc0_dir_pins: sdhc1-dir-pins {
+ function = "sdhc";
+ groups = "sdhc1-dir";
+ };
+
+ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
+ function = "gpio";
+ groups = "sdhc1-dir";
+ };
+
+ dspi2_cs31_pins: sdhc1-dir-spi3-pins {
+ function = "spi";
+ groups = "sdhc1-dir";
+ };
+
+ esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
+ function = "sdhc-data";
+ groups = "sdhc1-dir";
+ };
+
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ function = "gpio";
+ groups = "sdhc2-data74";
+ };
+
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ function = "i2c";
+ groups = "sdhc2-data74";
+ };
+
+ i2c0_pins: iic1-i2c-pins {
+ function = "i2c";
+ groups = "iic1";
+ };
+
+ gpio0_3_2_pins: iic1-gpio-pins {
+ function = "gpio";
+ groups = "iic1";
+ };
+ };
};
sfp: efuse at 1e80000 {
@@ -1531,179 +1727,6 @@ pcs18: ethernet-phy at 0 {
};
};
- pinmux_i2crv: pinmux at 70010012c {
- compatible = "pinctrl-single";
- reg = <0x00000007 0x0010012c 0x0 0xc>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <2>;
- pinctrl-single,bit-per-mux;
- pinctrl-single,register-width = <32>;
- pinctrl-single,function-mask = <0x7>;
-
- /* RCWSR12 */
- i2c1_pins: iic2-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 0x7>;
- };
-
- gpio0_31_30_pins: iic2-gpio-pins {
- pinctrl-single,bits = <0x0 0x1 0x7>;
- };
-
- ftm0_ch10_pins: iic2-ftm-pins {
- pinctrl-single,bits = <0x0 0x2 0x7>;
- };
-
- esdhc0_cd_wp_pins: iic2-sdhc-pins {
- pinctrl-single,bits = <0x0 0x6 0x7>;
- };
-
- i2c2_pins: iic3-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 3)>;
- };
-
- gpio0_29_28_pins: iic3-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
- };
-
- can0_pins: iic3-can-pins {
- pinctrl-single,bits = <0x0 (0x2 << 3) (0x7 << 3)>;
- };
-
- event65_pins: iic3-event-pins {
- pinctrl-single,bits = <0x0 (0x6 << 3) (0x7 << 3)>;
- };
-
- i2c3_pins: iic4-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 6)>;
- };
-
- gpio0_27_26_pins: iic4-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
- };
-
- can1_pins: iic4-can-pins {
- pinctrl-single,bits = <0x0 (0x2 << 6) (0x7 << 6)>;
- };
-
- event87_pins: iic4-event-pins {
- pinctrl-single,bits = <0x0 (0x6 << 6) (0x7 << 6)>;
- };
-
- i2c4_pins: iic5-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 9)>;
- };
-
- gpio0_25_24_pins: iic5-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
- };
-
- esdhc0_clksync_pins: iic5-sdhc-clk-pins {
- pinctrl-single,bits = <0x0 (0x2 << 9) (0x7 << 9)>;
- };
-
- dspi2_miso_mosi_pins: iic5-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 9) (0x7 << 9)>;
- };
-
- i2c5_pins: iic6-i2c-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 12)>;
- };
-
- gpio0_23_22_pins: iic6-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
- };
-
- esdhc1_clksync_pins: iic6-sdhc-clk-pins {
- pinctrl-single,bits = <0x0 (0x2 << 12) (0x7 << 12)>;
- };
-
- fspi_data74_pins: xspi1-data74-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
- };
-
- gpio1_31_28_pins: xspi1-data74-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 15) (0x7 << 15)>;
- };
-
- fspi_data30_pins: xspi1-data30-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
- };
-
- gpio1_27_24_pins: xspi1-data30-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 18) (0x7 << 18)>;
- };
-
- fspi_dqs_sck_cs10_pins: xspi1-base-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
- };
-
- gpio1_23_20_pins: xspi1-base-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 21) (0x7 << 21)>;
- };
-
- esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
- };
-
- gpio0_21_15_pins: sdhc1-base-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 24) (0x7 << 24)>;
- };
-
- dspi0_pins: sdhc1-base-spi1-pins {
- pinctrl-single,bits = <0x0 (0x2 << 24) (0x7 << 24)>;
- };
-
- esdhc0_cmd_data30_clk_dspi2_cs0_pins: sdhc1-base-sdhc-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 24) (0x7 << 24)>;
- };
-
- esdhc0_cmd_data30_clk_data4_pins: sdhc1-base-sdhc-data4-pins {
- pinctrl-single,bits = <0x0 (0x4 << 24) (0x7 << 24)>;
- };
-
- esdhc0_dir_pins: sdhc1-dir-pins {
- pinctrl-single,bits = <0x0 0x0 (0x7 << 27)>;
- };
-
- gpio0_14_12_pins: sdhc1-dir-gpio-pins {
- pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
- };
-
- dspi2_cs31_pins: sdhc1-dir-spi3-pins {
- pinctrl-single,bits = <0x0 (0x3 << 27) (0x7 << 27)>;
- };
-
- esdhc0_data75_pins: sdhc1-dir-sdhc-pins {
- pinctrl-single,bits = <0x0 (0x4 << 27) (0x7 << 27)>;
- };
-
- /* RCWSR13 */
- gpio1_18_15_pins: iic8-iic7-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
- };
-
- i2c6_i2c7_pins: iic8-iic7-i2c-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
- };
-
- /* RCWSR14 */
- /*
- * IIC1_PMUX is a single bit at RCWSR14[10], but bit-per-mux
- * uses the mask for the field to clear before applying the
- * value.
- * So bits 11 and 12, which are reserved, are written as 0
- * on every mux switch, it is harmless.
- */
- i2c0_pins: iic1-i2c-pins {
- pinctrl-single,bits = <0x8 0x0 (0x7 << 10)>;
- };
-
- gpio0_3_2_pins: iic1-gpio-pins {
- pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
- };
- };
-
fsl_mc: fsl-mc at 80c000000 {
compatible = "fsl,qoriq-mc";
reg = <0x00000008 0x0c000000 0 0x40>,
--
2.43.0
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