[PATCH v5 1/3] dt-bindings: usb: Add CIX Sky1 USBSSP controller
Hongliang Yang (杨宏亮)
hongliang.yang at cixtech.com
Mon Nov 2 23:49:36 PST 2026
Add device tree binding for the CIX Sky1 Cadence USBSSP controller
glue layer. Each controller has an AXI bus attribute configuration
register and a controller status register. The glue registers of the
two controllers are interleaved inside a shared RCSU region, which is
represented as a simple-bus container node with an address-translating
ranges property; each glue node describes its registers as offsets
inside that region. Mode strap controls are programmed through the
Sky1 S5 system controller referenced by the cix,usb-syscon phandle.
The CIX glue node wraps a Cadence USBSSP core as a child node.
Signed-off-by: Hongliang Yang <hongliang.yang at cixtech.com>
---
v4 -> v5:
- Added the MAINTAINERS entry for the glue driver.
.../bindings/usb/cix,sky1-usbssp.yaml | 152 ++++++++++++++++++
MAINTAINERS | 2 +
2 files changed, 154 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
new file mode 100644
index 000000000000..c29654567e76
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/cix,sky1-usbssp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CIX Sky1 Cadence USBSSP Controller
+
+maintainers:
+ - Hongliang Yang <hongliang.yang at cixtech.com>
+
+description:
+ The CIX Sky1 USBSSP controller is based on the Cadence USBSSP DRD
+ controller. The integration adds per-controller glue registers in the
+ SoC system control aperture, an AXI bus attribute configuration
+ register and a controller status register, both mapped by the reg
+ property of the glue node. The glue registers of the two controllers
+ are interleaved inside a shared RCSU region, which is represented as
+ a simple-bus container node with an address-translating ranges
+ property; each glue node describes its registers as offsets inside
+ that region. Mode strap controls are programmed through the Sky1 S5
+ system controller referenced by the cix,usb-syscon phandle. The CIX
+ glue node wraps a Cadence USBSSP core as a child node.
+
+properties:
+ compatible:
+ const: cix,sky1-usbssp
+
+ reg:
+ items:
+ - description: AXI bus attribute configuration registers
+ - description: Controller status registers
+
+ reg-names:
+ items:
+ - const: axi
+ - const: status
+
+ clocks:
+ items:
+ - description: Start-of-frame clock
+ - description: AXI bus clock
+ - description: Low-power mode clock
+ - description: APB register interface clock
+
+ clock-names:
+ items:
+ - const: sof
+ - const: axi
+ - const: lpm
+ - const: apb
+
+ resets:
+ items:
+ - description: APB register reset
+ - description: Controller reset
+
+ reset-names:
+ items:
+ - const: apb
+ - const: core
+
+ cix,usb-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the Sky1 S5 system controller used to program USB mode
+ strap controls.
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+patternProperties:
+ "^usb@[0-9a-f]+$":
+ $ref: cdns,usb3.yaml#
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - cix,usb-syscon
+ - "#address-cells"
+ - "#size-cells"
+ - ranges
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/cix,sky1.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/cix,sky1-s5-system-control.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ usb-rcsu at 91c0300 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x00000000 0x00 0x091c0300 0x00 0x150>,
+ <0x00 0x091d0000 0x00 0x091d0000 0x00 0x20000>;
+
+ usb at 14 {
+ compatible = "cix,sky1-usbssp";
+ reg = <0x00 0x14 0x00 0x10>,
+ <0x00 0x100 0x00 0x10>;
+ reg-names = "axi", "status";
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&scmi_clk CLK_TREE_USB3A_H0_CLK_SOF>,
+ <&scmi_clk CLK_TREE_USB3A_0_AXI_GATE>,
+ <&scmi_clk CLK_TREE_USB3A_H0_CLK_LPM>,
+ <&scmi_clk CLK_TREE_USB3A_0_APB_GATE>;
+ clock-names = "sof", "axi", "lpm", "apb";
+ resets = <&src SKY1_USBC_SS2_PRST_N>,
+ <&src SKY1_USBC_SS2_RST_N>;
+ reset-names = "apb", "core";
+ cix,usb-syscon = <&src>;
+
+ usb at 91d0000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x91d0000 0x00 0x4000>,
+ <0x00 0x91d8000 0x00 0x8000>,
+ <0x00 0x91d4000 0x00 0x4000>;
+ reg-names = "otg", "xhci", "dev";
+ dr_mode = "otg";
+
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
+ maximum-speed = "super-speed-plus";
+
+ phys = <&usb3_phy4_0>, <&usb2_phy6>;
+ phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
+ };
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index b857e529e5e2..92ff4ccff791 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2904,9 +2904,11 @@ T: git https://github.com/cixtech/linux-mainline.git
F: Documentation/devicetree/bindings/arm/cix.yaml
F: Documentation/devicetree/bindings/mailbox/cix,sky1-mbox.yaml
F: Documentation/devicetree/bindings/phy/cix,sky1-usb3-phy.yaml
+F: Documentation/devicetree/bindings/usb/cix,sky1-usbssp.yaml
F: arch/arm64/boot/dts/cix/
F: drivers/mailbox/cix-mailbox.c
F: drivers/phy/cix/
+F: drivers/usb/cdns3/cdnsp-sky1.*
K: \bcix\b
ARM/CLKDEV SUPPORT
--
2.54.0
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