[PATCH 1/2] dt-bindings: dma: nuvoton,ma35d1-pdma: Document MA35D1 PDMA controller
Shan-Chun Hung
shanchun1218 at gmail.com
Mon Nov 2 18:22:01 PST 2026
Add binding for Nuvoton MA35D1 PDMA controller.
Signed-off-by: Shan-Chun Hung <shanchun1218 at gmail.com>
---
.../bindings/dma/nuvoton,ma35d1-pdma.yaml | 72 +++++++++++
include/dt-bindings/dma/ma35d1-pdma.h | 113 ++++++++++++++++++
2 files changed, 185 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml
create mode 100644 include/dt-bindings/dma/ma35d1-pdma.h
diff --git a/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml b/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml
new file mode 100644
index 000000000000..cd752571242c
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nuvoton,ma35d1-pdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 PDMA controller
+
+description:
+ This describes the devicetree bindings for four Peripheral DMA engines to perform
+ memory-to-memory, memory-to-peripheral, or peripheral-to-memory data transfer
+ capable of supporting 10 channels, implemented in Nuvoton MA35D1 SoCs.
+
+maintainers:
+ - Shan-Chun Hung <shanchun1218 at gmail.com>
+
+allOf:
+ - $ref: dma-controller.yaml#
+
+properties:
+ compatible:
+ const: nuvoton,ma35d1-pdma
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#dma-cells":
+ const: 2
+ description:
+ The first cell is the channel number. The second cell is the
+ peripheral request source (REQSRC) selection, which defines which
+ peripheral is connected to that PDMA channel.
+
+ dma-channels:
+ const: 10
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - "#dma-cells"
+ - dma-channels
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-controller at 40080000 {
+ compatible = "nuvoton,ma35d1-pdma";
+ reg = <0x0 0x40080000 0x0 0x2000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk PDMA0_GATE>;
+ #dma-cells = <2>;
+ dma-channels = <10>;
+ };
+ };
+
+...
diff --git a/include/dt-bindings/dma/ma35d1-pdma.h b/include/dt-bindings/dma/ma35d1-pdma.h
new file mode 100644
index 000000000000..0ddc99d29661
--- /dev/null
+++ b/include/dt-bindings/dma/ma35d1-pdma.h
@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Nuvoton Technology Corp.
+ */
+
+#ifndef __DT_BINDINGS_DMA_MA35D1_PDMA_H__
+#define __DT_BINDINGS_DMA_MA35D1_PDMA_H__
+
+#define MA35D1_PDMA_MEM 0
+#define MA35D1_PDMA_UART0_TX 4
+#define MA35D1_PDMA_UART0_RX 5
+#define MA35D1_PDMA_UART1_TX 6
+#define MA35D1_PDMA_UART1_RX 7
+#define MA35D1_PDMA_UART2_TX 8
+#define MA35D1_PDMA_UART2_RX 9
+#define MA35D1_PDMA_UART3_TX 10
+#define MA35D1_PDMA_UART3_RX 11
+#define MA35D1_PDMA_UART4_TX 12
+#define MA35D1_PDMA_UART4_RX 13
+#define MA35D1_PDMA_UART5_TX 14
+#define MA35D1_PDMA_UART5_RX 15
+#define MA35D1_PDMA_UART6_TX 16
+#define MA35D1_PDMA_UART6_RX 17
+#define MA35D1_PDMA_UART7_TX 18
+#define MA35D1_PDMA_UART7_RX 19
+#define MA35D1_PDMA_UART8_TX 20
+#define MA35D1_PDMA_UART8_RX 21
+#define MA35D1_PDMA_UART9_TX 22
+#define MA35D1_PDMA_UART9_RX 23
+#define MA35D1_PDMA_UART10_TX 24
+#define MA35D1_PDMA_UART10_RX 25
+#define MA35D1_PDMA_UART11_TX 26
+#define MA35D1_PDMA_UART11_RX 27
+#define MA35D1_PDMA_UART12_TX 28
+#define MA35D1_PDMA_UART12_RX 29
+#define MA35D1_PDMA_UART13_TX 30
+#define MA35D1_PDMA_UART13_RX 31
+#define MA35D1_PDMA_UART14_TX 32
+#define MA35D1_PDMA_UART14_RX 33
+#define MA35D1_PDMA_UART15_TX 34
+#define MA35D1_PDMA_UART15_RX 35
+#define MA35D1_PDMA_UART16_TX 36
+#define MA35D1_PDMA_UART16_RX 37
+#define MA35D1_PDMA_QSPI0_TX 54
+#define MA35D1_PDMA_QSPI0_RX 55
+#define MA35D1_PDMA_QSPI1_TX 56
+#define MA35D1_PDMA_QSPI1_RX 57
+#define MA35D1_PDMA_SPI0_TX 60
+#define MA35D1_PDMA_SPI0_RX 61
+#define MA35D1_PDMA_SPI1_TX 62
+#define MA35D1_PDMA_SPI1_RX 63
+#define MA35D1_PDMA_SPI2_TX 64
+#define MA35D1_PDMA_SPI2_RX 65
+#define MA35D1_PDMA_SPI3_TX 66
+#define MA35D1_PDMA_SPI3_RX 67
+#define MA35D1_PDMA_I2C0_TX 70
+#define MA35D1_PDMA_I2C0_RX 71
+#define MA35D1_PDMA_I2C1_TX 72
+#define MA35D1_PDMA_I2C1_RX 73
+#define MA35D1_PDMA_I2C2_TX 74
+#define MA35D1_PDMA_I2C2_RX 75
+#define MA35D1_PDMA_I2C3_TX 76
+#define MA35D1_PDMA_I2C3_RX 77
+#define MA35D1_PDMA_I2C4_TX 78
+#define MA35D1_PDMA_I2C4_RX 79
+#define MA35D1_PDMA_I2C5_TX 80
+#define MA35D1_PDMA_I2C5_RX 81
+#define MA35D1_PDMA_I2S0_TX 86
+#define MA35D1_PDMA_I2S0_RX 87
+#define MA35D1_PDMA_I2S1_TX 88
+#define MA35D1_PDMA_I2S1_RX 89
+#define MA35D1_PDMA_TMR0 94
+#define MA35D1_PDMA_TMR1 95
+#define MA35D1_PDMA_TMR2 96
+#define MA35D1_PDMA_TMR3 97
+#define MA35D1_PDMA_TMR4 98
+#define MA35D1_PDMA_TMR5 99
+#define MA35D1_PDMA_TMR6 100
+#define MA35D1_PDMA_TMR7 101
+#define MA35D1_PDMA_TMR8 102
+#define MA35D1_PDMA_TMR9 103
+#define MA35D1_PDMA_TMR10 104
+#define MA35D1_PDMA_TMR11 105
+#define MA35D1_PDMA_EPWM0_P1_RX 110
+#define MA35D1_PDMA_EPWM0_P2_RX 111
+#define MA35D1_PDMA_EPWM0_P3_RX 112
+#define MA35D1_PDMA_EPWM1_P1_RX 113
+#define MA35D1_PDMA_EPWM1_P2_RX 114
+#define MA35D1_PDMA_EPWM1_P3_RX 115
+#define MA35D1_PDMA_EPWM2_P1_RX 116
+#define MA35D1_PDMA_EPWM2_P2_RX 117
+#define MA35D1_PDMA_EPWM2_P3_RX 118
+#define MA35D1_PDMA_EPWM0_CH0_TX 122
+#define MA35D1_PDMA_EPWM0_CH1_TX 123
+#define MA35D1_PDMA_EPWM0_CH2_TX 124
+#define MA35D1_PDMA_EPWM0_CH3_TX 125
+#define MA35D1_PDMA_EPWM0_CH4_TX 126
+#define MA35D1_PDMA_EPWM0_CH5_TX 127
+#define MA35D1_PDMA_EPWM1_CH0_TX 128
+#define MA35D1_PDMA_EPWM1_CH1_TX 129
+#define MA35D1_PDMA_EPWM1_CH2_TX 130
+#define MA35D1_PDMA_EPWM1_CH3_TX 131
+#define MA35D1_PDMA_EPWM1_CH4_TX 132
+#define MA35D1_PDMA_EPWM1_CH5_TX 133
+#define MA35D1_PDMA_EPWM2_CH0_TX 134
+#define MA35D1_PDMA_EPWM2_CH1_TX 135
+#define MA35D1_PDMA_EPWM2_CH2_TX 136
+#define MA35D1_PDMA_EPWM2_CH3_TX 137
+#define MA35D1_PDMA_EPWM2_CH4_TX 138
+#define MA35D1_PDMA_EPWM2_CH5_TX 139
+#define MA35D1_PDMA_EADC0_RX 146
+
+#endif /* __DT_BINDINGS_DMA_MA35D1_PDMA_H__ */
--
2.25.1
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