[PATCH v2 03/16] KVM: arm64: gic-v5: Share CoreSight ID register emulation
Sascha Bischoff
sascha.bischoff at arm.com
Mon Nov 2 11:44:41 PST 2026
The GICv5 IRS and ITS expose the same CoreSight identification register
block. Move the register-value switch into a shared helper and describe
the contiguous ID register range with one register-region descriptor.
This keeps the IRS behaviour unchanged while giving the ITS MMIO
emulation a helper it can reuse when it is added in the following commit.
Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
---
arch/arm64/kvm/vgic/vgic-irs-v5.c | 75 +++---------------------------
arch/arm64/kvm/vgic/vgic-v5.c | 34 ++++++++++++++
arch/arm64/kvm/vgic/vgic.h | 1 +
include/linux/irqchip/arm-gic-v5.h | 2 +
4 files changed, 44 insertions(+), 68 deletions(-)
diff --git a/arch/arm64/kvm/vgic/vgic-irs-v5.c b/arch/arm64/kvm/vgic/vgic-irs-v5.c
index 8d0ad74ebc64a..d0ebed2e1663b 100644
--- a/arch/arm64/kvm/vgic/vgic-irs-v5.c
+++ b/arch/arm64/kvm/vgic/vgic-irs-v5.c
@@ -520,38 +520,9 @@ static void vgic_v5_mmio_write_irs_ist(struct kvm_vcpu *vcpu, gpa_t addr,
static unsigned long vgic_v5_coresight_read(struct kvm_vcpu *vcpu,
gpa_t addr, unsigned int len)
{
- const size_t offset = addr & (SZ_64K - 1);
+ u32 offset = addr & (SZ_64K - 1);
- switch (offset) {
- case GICV5_CORESIGHT_DEVARCH:
- return GICV5_CORESIGHT_DEVARCH_VAL;
- case GICV5_CORESIGHT_PIDR4:
- return GICV5_CORESIGHT_PIDR4_JEP106_CONT;
- case GICV5_CORESIGHT_PIDR5:
- return GICV5_CORESIGHT_PIDR5_RES0;
- case GICV5_CORESIGHT_PIDR6:
- return GICV5_CORESIGHT_PIDR6_RES0;
- case GICV5_CORESIGHT_PIDR7:
- return GICV5_CORESIGHT_PIDR7_RES0;
- case GICV5_CORESIGHT_PIDR0:
- return GICV5_CORESIGHT_PIDR0_PART_0;
- case GICV5_CORESIGHT_PIDR1:
- return GICV5_CORESIGHT_PIDR1_DES_0_PART_1;
- case GICV5_CORESIGHT_PIDR2:
- return GICV5_CORESIGHT_PIDR2_DES_1;
- case GICV5_CORESIGHT_PIDR3:
- return GICV5_CORESIGHT_PIDR3_REVAND_CMOD;
- case GICV5_CORESIGHT_CIDR0:
- return GICV5_CORESIGHT_CIDR0_VAL;
- case GICV5_CORESIGHT_CIDR1:
- return GICV5_CORESIGHT_CIDR1_VAL;
- case GICV5_CORESIGHT_CIDR2:
- return GICV5_CORESIGHT_CIDR2_VAL;
- case GICV5_CORESIGHT_CIDR3:
- return GICV5_CORESIGHT_CIDR3_VAL;
- default:
- return 0;
- }
+ return vgic_v5_handle_guest_coresight_idreg_read(offset);
}
static unsigned long vgic_v5_mmio_uaccess_read_irs_status(struct kvm_vcpu *vcpu,
@@ -903,45 +874,13 @@ static const struct vgic_register_region vgic_v5_irs_registers[] = {
vgic_mmio_read_raz, vgic_mmio_write_wi, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
- /* CoreSight identification registers */
+ /* Split the ranges so KVM_HAS_DEVICE_ATTR only reports actual registers. */
REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_DEVARCH,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
+ vgic_v5_coresight_read, vgic_mmio_write_wi,
+ 4, VGIC_ACCESS_32bit),
REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR4,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR5,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR6,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR7,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR0,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR1,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR2,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_PIDR3,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_CIDR0,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_CIDR1,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_CIDR2,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
- VGIC_ACCESS_32bit),
- REGISTER_DESC_WITH_LENGTH(GICV5_CORESIGHT_CIDR3,
- vgic_v5_coresight_read, vgic_mmio_write_wi, 4,
+ vgic_v5_coresight_read, vgic_mmio_write_wi,
+ GICV5_CORESIGHT_PIDR_CIDR_SIZE,
VGIC_ACCESS_32bit),
};
diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c
index 91810fbd99afa..18184020e188b 100644
--- a/arch/arm64/kvm/vgic/vgic-v5.c
+++ b/arch/arm64/kvm/vgic/vgic-v5.c
@@ -1601,3 +1601,37 @@ int vgic_v5_irs_restore_ists(struct kvm *kvm, struct kvm_device_attr *attr)
return ret;
}
+
+unsigned long vgic_v5_handle_guest_coresight_idreg_read(u32 offset)
+{
+ switch (offset) {
+ case GICV5_CORESIGHT_DEVARCH:
+ return GICV5_CORESIGHT_DEVARCH_VAL;
+ case GICV5_CORESIGHT_PIDR4:
+ return GICV5_CORESIGHT_PIDR4_JEP106_CONT;
+ case GICV5_CORESIGHT_PIDR5:
+ return GICV5_CORESIGHT_PIDR5_RES0;
+ case GICV5_CORESIGHT_PIDR6:
+ return GICV5_CORESIGHT_PIDR6_RES0;
+ case GICV5_CORESIGHT_PIDR7:
+ return GICV5_CORESIGHT_PIDR7_RES0;
+ case GICV5_CORESIGHT_PIDR0:
+ return GICV5_CORESIGHT_PIDR0_PART_0;
+ case GICV5_CORESIGHT_PIDR1:
+ return GICV5_CORESIGHT_PIDR1_DES_0_PART_1;
+ case GICV5_CORESIGHT_PIDR2:
+ return GICV5_CORESIGHT_PIDR2_DES_1;
+ case GICV5_CORESIGHT_PIDR3:
+ return GICV5_CORESIGHT_PIDR3_REVAND_CMOD;
+ case GICV5_CORESIGHT_CIDR0:
+ return GICV5_CORESIGHT_CIDR0_VAL;
+ case GICV5_CORESIGHT_CIDR1:
+ return GICV5_CORESIGHT_CIDR1_VAL;
+ case GICV5_CORESIGHT_CIDR2:
+ return GICV5_CORESIGHT_CIDR2_VAL;
+ case GICV5_CORESIGHT_CIDR3:
+ return GICV5_CORESIGHT_CIDR3_VAL;
+ default:
+ return 0;
+ }
+}
diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h
index 8792953057bb7..f95eec6a01f63 100644
--- a/arch/arm64/kvm/vgic/vgic.h
+++ b/arch/arm64/kvm/vgic/vgic.h
@@ -390,6 +390,7 @@ int vgic_v5_probe(const struct gic_kvm_info *info);
void vgic_v5_reset(struct kvm_vcpu *vcpu);
int vgic_v5_init(struct kvm *kvm);
int kvm_vgic_v5_irs_init(struct kvm *kvm, unsigned int nr_spis);
+unsigned long vgic_v5_handle_guest_coresight_idreg_read(u32 offset);
void vgic_v5_teardown(struct kvm *kvm);
int vgic_v5_map_resources(struct kvm *kvm);
void vgic_v5_set_ppi_ops(struct kvm_vcpu *vcpu, u32 vintid);
diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h
index 299e75bc95255..ee3677413560f 100644
--- a/include/linux/irqchip/arm-gic-v5.h
+++ b/include/linux/irqchip/arm-gic-v5.h
@@ -498,6 +498,8 @@
#define GICV5_CORESIGHT_CIDR1 0xfff4
#define GICV5_CORESIGHT_CIDR2 0xfff8
#define GICV5_CORESIGHT_CIDR3 0xfffc
+#define GICV5_CORESIGHT_PIDR_CIDR_SIZE \
+ (GICV5_CORESIGHT_CIDR3 + 4 - GICV5_CORESIGHT_PIDR4)
#define GICV5_CORESIGHT_DEVARCH_VAL \
(FIELD_PREP(GENMASK(31, 21), 0x23b) | \
--
2.34.1
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