[PATCH 02/10] irqchip/gic-v5: Only set IRS DPS when 1ofN routing is supported

[Lorenzo Pieralisi]

On Mon, Nov 02, 2026 at 01:32:55PM +0000, Sascha Bischoff wrote:
> IRS_PE_CR0.DPS is RES0 when the IRS does not support 1ofN routing.
> Read the capability from IRS_IDR0 and skip programming DPS on systems
> without support for 1ofN routing, rather than blindly writing it.
> 
> Fixes: 5cb1b6dab2def ("irqchip/gic-v5: Add GICv5 IRS/SPI support")
> Signed-off-by: Sascha Bischoff <sascha.bischoff at arm.com>
> ---
>  drivers/irqchip/irq-gic-v5-irs.c   | 14 +++++++++-----
>  include/linux/irqchip/arm-gic-v5.h |  1 +
>  2 files changed, 10 insertions(+), 5 deletions(-)

Acked-by: Lorenzo Pieralisi <lpieralisi at kernel.org>

> diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c
> index 9d60f474aa4f6..4edf787f3f97f 100644
> --- a/drivers/irqchip/irq-gic-v5-irs.c
> +++ b/drivers/irqchip/irq-gic-v5-irs.c
> @@ -541,12 +541,15 @@ int gicv5_irs_register_cpu(int cpuid)
>  		return -ENXIO;
>  	}
>  
> -	cr0 = FIELD_PREP(GICV5_IRS_PE_CR0_DPS, 0x1);
> -	irs_writel_relaxed(irs_data, cr0, GICV5_IRS_PE_CR0);
> +	/* IRS_PE_CR0.DPS is RES0 when 1ofN routing is unsupported. */
> +	if (gicv5_global_data.one_of_n) {
> +		cr0 = FIELD_PREP(GICV5_IRS_PE_CR0_DPS, 0x1);
> +		irs_writel_relaxed(irs_data, cr0, GICV5_IRS_PE_CR0);
>  
> -	ret = gicv5_irs_wait_for_pe_cr0(irs_data);
> -	if (ret)
> -		return ret;
> +		ret = gicv5_irs_wait_for_pe_cr0(irs_data);
> +		if (ret)
> +			return ret;
> +	}
>  
>  	pr_debug("CPU %d enabled PE IAFFID 0x%x\n", cpuid, iaffid);
>  
> @@ -725,6 +728,7 @@ static int __init gicv5_irs_init(struct gicv5_irs_chip_data *irs_data)
>  	if (list_empty(&irs_nodes)) {
>  		idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0);
>  		gicv5_global_data.virt_capable = !!FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);
> +		gicv5_global_data.one_of_n = !!FIELD_GET(GICV5_IRS_IDR0_ONE_N, idr);
>  
>  		idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);
>  		irs_setup_pri_bits(idr);
> diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h
> index 299e75bc95255..34e22e7d4a4c7 100644
> --- a/include/linux/irqchip/arm-gic-v5.h
> +++ b/include/linux/irqchip/arm-gic-v5.h
> @@ -532,6 +532,7 @@ struct gicv5_chip_data {
>  	u8			cpuif_id_bits;
>  	u8			irs_pri_bits;
>  	bool			virt_capable;
> +	bool			one_of_n;
>  	struct {
>  		__le64 *l1ist_addr;
>  		u32 l2_size;
> 
> -- 
> 2.34.1
>