[PATCH v2] drm/bridge: dw-mipi-dsi: let the glue compute the hcomponent lbcc
Romain TISSERAND
romain.tisserand at gmail.com
Sun Nov 1 06:30:31 PST 2026
Commit ac87d23694f4 ("drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock
rate to calculate lbcc") counts HSA, HBP and HLINE from the pixel clock,
which is only right when the lanes run at the pixel bandwidth (pixel
clock * bpp / lanes). Commit 93e82bb4de01 ("drm/bridge: synopsys:
dw-mipi-dsi: Fix hcomponent lbcc for burst mode") went back to the lane
rate for burst mode, where the lanes are faster on purpose.
The Rockchip glue runs the lanes faster in every mode: at 1.25 times
(bpp / lanes, rounded down) times the pixel clock, or 1000 Mbps, above
the pixel bandwidth. In non-burst video mode the line programmed in lane
byte clocks is then shorter than the DPI line. On the GPD XD (RK3288,
ILI9881C panel, 4 lanes at 448 Mbps, 59.5 MHz pixel clock, htotal 747)
HLINE was 561 lane byte clocks (10.0 us) for a 12.55 us line, and the
panel shows garbage as soon as a client page-flips.
The glue picks the lane rate, so let it compute the lane byte clock
cycles too: add an optional get_hcomponent_lbcc() callback to
dw_mipi_dsi_plat_data, and implement it in the Rockchip glue from the
lane rate. Glues without it (i.MX93, Meson, STM) keep the current
computation, and so does Rockchip dual-DSI, which this hasn't been
tested on. On the GPD XD this gives HLINE 704, HSA 13 and HBP 4, and
the picture is stable.
Fixes: ac87d23694f4 ("drm/bridge: synopsys: dw-mipi-dsi: Use pixel clock rate to calculate lbcc")
Signed-off-by: Romain TISSERAND <romain.tisserand at gmail.com>
---
Changes in v2:
- Drop the 1/8 threshold: the glue now computes the lane byte clock
cycles through a new optional get_hcomponent_lbcc() callback in
dw_mipi_dsi_plat_data, and the Rockchip glue implements it from its
lane rate (Chaoyi Chen). This also covers RGB666 packed on 4 lanes,
which the 1/8 slack missed (Sashiko).
- Rockchip dual-DSI keeps the core computation: the lane rate would
change the timing of the dual-DSI Gru Scarlet panels (innolux,p097pfg,
non-burst, 4+4 lanes), which I can't test.
- Commit message: the Rockchip glue doesn't follow a panel rate in
mainline, and the GPD XD numbers are now those of the rate it picks
(448 Mbps).
- v1: https://lore.kernel.org/all/20261025142639.3454322-1-romain.tisserand@gmail.com/
Notes for reviewers (not for the changelog):
- The callback returns 0 to let the core compute the value, so a glue
can implement it for some configurations only (Rockchip: single DSI).
- Testing: built with W=1 for arm (multi_v7) and arm64 (defconfig),
DRM_DW_MIPI_DSI=y and =m, together with the Meson and i.MX93 glues, no
warnings. Tested live on the GPD XD (RK3288, ILI9881C, non-burst with
sync pulses, 4 lanes at 448 Mbps) on 6.18.54 with this exact change:
without it HLINE 561, HSA 10, HBP 3 and garbage on screen as soon as
the UI page-flips; with it HLINE 704, HSA 13, HBP 4 and a clean, stable
picture in the UI and in games. Not tested on i.MX93, Meson, STM or
Rockchip dual-DSI hardware; their computation is unchanged.
- Tool disclosure: this patch was prepared with Claude Opus 5.5
(Anthropic) as a coding assistant, in an interactive session where I
asked it to bring up the GPD XD display and then to prepare the fix
for upstream. It located the cause from the DSI host registers, went
through the history of the lbcc computation (ac87d23694f4,
93e82bb4de01) and the lane rates of the other dw-mipi-dsi glues, and
drafted the code change and the changelog; v2 follows the reviews of
Chaoyi Chen and Sashiko. I reviewed and understand both, and tested
the patch on the GPD XD as described above.
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 39 ++++++++++++-------
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 23 +++++++++++
include/drm/bridge/dw_mipi_dsi.h | 10 +++++
3 files changed, 57 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 22d1b8cbe1..b7578265ca 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -780,28 +780,37 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
const struct drm_display_mode *mode,
u32 hcomponent)
{
+ const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
u32 frac, lbcc, minimum_lbcc;
int bpp;
- if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
- /* lbcc based on lane_mbps */
- lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
- } else {
- /* lbcc based on pixel clock rate */
- bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
- if (bpp < 0) {
- dev_err(dsi->dev, "failed to get bpp\n");
- return 0;
+ lbcc = 0;
+ if (pdata->get_hcomponent_lbcc)
+ lbcc = pdata->get_hcomponent_lbcc(pdata->priv_data, mode,
+ hcomponent);
+
+ if (!lbcc) {
+ if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) {
+ /* lbcc based on lane_mbps */
+ lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
+ } else {
+ /* lbcc based on pixel clock rate */
+ bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
+ if (bpp < 0) {
+ dev_err(dsi->dev, "failed to get bpp\n");
+ return 0;
+ }
+
+ lbcc = div_u64((u64)hcomponent * mode->clock * bpp,
+ dsi->lanes * 8);
}
- lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8);
+ frac = lbcc % mode->clock;
+ lbcc = lbcc / mode->clock;
+ if (frac)
+ lbcc++;
}
- frac = lbcc % mode->clock;
- lbcc = lbcc / mode->clock;
- if (frac)
- lbcc++;
-
minimum_lbcc = dw_mipi_dsi_get_minimum_lbcc(dsi);
if (lbcc < minimum_lbcc)
diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
index aab3353945..57ebb3a59f 100644
--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
@@ -771,6 +771,28 @@ dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
return dw_mipi_dsi_phy_px30_get_timing(dsi, lane_mbps, timing);
}
+/*
+ * dw_mipi_dsi_get_lane_mbps() runs the lanes faster than the pixel bandwidth
+ * in every video mode, not only in burst mode: count the horizontal timings
+ * from the lane rate, or the line is shorter than the DPI line.
+ *
+ * Dual-DSI keeps the core computation (return 0): the lane rate would change
+ * the timing of the dual-DSI panels in use, and that hasn't been tested.
+ */
+static u32
+dw_mipi_dsi_rockchip_get_hcomponent_lbcc(void *priv_data,
+ const struct drm_display_mode *mode,
+ u32 hcomponent)
+{
+ struct dw_mipi_dsi_rockchip *dsi = priv_data;
+
+ if (dsi->slave || dsi->is_slave)
+ return 0;
+
+ return DIV_ROUND_UP_ULL((u64)hcomponent * dsi->lane_mbps *
+ MSEC_PER_SEC / 8, mode->clock);
+}
+
static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = {
.init = dw_mipi_dsi_phy_init,
.power_on = dw_mipi_dsi_phy_power_on,
@@ -1494,6 +1516,7 @@ static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev)
dsi->dev = dev;
dsi->pdata.base = dsi->base;
dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes;
+ dsi->pdata.get_hcomponent_lbcc = dw_mipi_dsi_rockchip_get_hcomponent_lbcc;
dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops;
dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops;
dsi->pdata.priv_data = dsi;
diff --git a/include/drm/bridge/dw_mipi_dsi.h b/include/drm/bridge/dw_mipi_dsi.h
index 65d5e68065..6580c16d80 100644
--- a/include/drm/bridge/dw_mipi_dsi.h
+++ b/include/drm/bridge/dw_mipi_dsi.h
@@ -62,6 +62,16 @@ struct dw_mipi_dsi_plat_data {
bool (*mode_fixup)(void *priv_data, const struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode);
+ /*
+ * Optional: number of lane byte clock cycles for @hcomponent pixels
+ * of @mode, for glues whose lanes don't run at the pixel bandwidth.
+ * Without it, or when it returns 0, the core uses the lane rate in
+ * burst mode and the pixel clock otherwise.
+ */
+ u32 (*get_hcomponent_lbcc)(void *priv_data,
+ const struct drm_display_mode *mode,
+ u32 hcomponent);
+
u32 *(*get_input_bus_fmts)(void *priv_data,
struct drm_bridge *bridge,
struct drm_bridge_state *bridge_state,
base-commit: cf61bef3801c3c9d0d8c39026b7b2fb242898a3a
--
2.43.0
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