[PATCH v2 10/18] arm64: sysreg: Add FPCR and FPSR

[Vladimir Murzin]

On 5/28/26 17:54, Mark Rutland wrote:
> Add sysreg definitions for FPCR and FPSR.
> 
> Some versions of LLVM will refuse to assemble accesses to FPCR and FPSR
> unless the "fp" arch extension is enabled, which we don't currently do
> for read_sysreg() and write_sysreg(). In general, handling feature
> dependencies would complicate read_sysreg() and write_sysreg(), and it's
> simpler to use read_sysreg_s() and write_sysreg_s() instead, requiring
> sysreg definitions.
> 
> The values used can be found in ARM ARM issue M.b:
> 
>   https://developer.arm.com/documentation/ddi0487/mb/
> 
> ... in sections:
> 
> * C5.2.8 ("FPCR, Floating-point Control Register")
> * C5.2.10 ("FPSR, Floating-point Status Register")
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Fuad Tabba <tabba at google.com>
> Cc: James Morse <james.morse at arm.com>
> Cc: Marc Zyngier <maz at kernel.org>
> Cc: Mark Brown <broonie at kernel.org>
> Cc: Oliver Upton <oupton at kernel.org>
> Cc: Will Deacon <will at kernel.org>
> ---
>  arch/arm64/tools/sysreg | 45 +++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 45 insertions(+)
> 
> diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
> index 6c3ff14e561e6..8b219d6566608 100644
> --- a/arch/arm64/tools/sysreg
> +++ b/arch/arm64/tools/sysreg
> @@ -3790,6 +3790,51 @@ Field	1	ZA
>  Field	0	SM
>  EndSysreg
>  
> +Sysreg	FPCR	3	3	4	4	0
> +Res0	63:27
> +Field	26	AHP
> +Field	25	DN
> +Field	24	FZ
> +Enum	23:22	RMode
> +	0b00	RN
> +	0b01	RP
> +	0b10	RM
> +	0b11	RZ
> +EndEnum
> +Field	21:20	Stride
> +Field	19	FZ16
> +Field	18:16	Len
> +Field	15	IDE
> +Res0	14
> +Field	13	EBF
> +Field	12	IXE
> +Field	11	UFE
> +Field	10	OFE
> +Field	9	DZE
> +Field	8	IOE
> +Res0	7:3
> +Field	2	NEP
> +Field	1	AH
> +Field	0	FIZ
> +EndSysreg
> +
> +Sysreg	FPSR	3	3	4	4	1
> +Res0	63:32
> +Field	31	N
> +Field	30	Z
> +Field	29	C
> +Field	28	V
> +Field	27	QC
> +Res0	26:8
> +Field	7	IDC
> +Res0	6:5
> +Field	4	IXC
> +Field	3	UFC
> +Field	2	OFC
> +Field	1	DZC
> +Field	0	IOC
> +EndSysreg
> +
>  Sysreg	FPMR	3	3	4	4	2
>  Res0	63:38
>  Field	37:32	LSCALE2
> -- 2.30.2
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin at arm.com>