[PATCH v2 07/18] arm64: fpsimd: Use assembler for SVE instructions

[Vladimir Murzin]

On 5/28/26 17:54, Mark Rutland wrote:
> Historically we supported assemblers which could not assemble SVE
> instructions. We dropped support for such assemblers in commit:
> 
>   118c40b7b503 ("kbuild: require gcc-8 and binutils-2.30")
> 
> Since that commit, all supported assemblers (binutils and LLVM) are
> capable of assembling SVE instructions, and there's no need for us to
> manually encode SVE instructions.
> 
> Rely on the assembler to encode SVE instructions, and remove the manual
> encoding. The various _sve_<insn> macros are kept for now, and will be
> cleaned up in subsequent patches.
> 
> There should be no functional change as a result of this patch.
> 
> Signed-off-by: Mark Rutland <mark.rutland at arm.com>
> Reviewed-by: Mark Brown <broonie at kernel.org>
> Cc: Catalin Marinas <catalin.marinas at arm.com>
> Cc: Fuad Tabba <tabba at google.com>
> Cc: James Morse <james.morse at arm.com>
> Cc: Marc Zyngier <maz at kernel.org>
> Cc: Oliver Upton <oupton at kernel.org>
> Cc: Will Deacon <will at kernel.org>
> ---
>  arch/arm64/include/asm/fpsimdmacros.h | 65 +++++++--------------------
>  1 file changed, 17 insertions(+), 48 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/fpsimdmacros.h b/arch/arm64/include/asm/fpsimdmacros.h
> index adf33d2da40c3..4ba23e493cb69 100644
> --- a/arch/arm64/include/asm/fpsimdmacros.h
> +++ b/arch/arm64/include/asm/fpsimdmacros.h
> @@ -99,85 +99,54 @@
>  	.endif
>  .endm
>  
> -/* SVE instruction encodings for non-SVE-capable assemblers */
> -/* (pre binutils 2.28, all kernel capable clang versions support SVE) */
> +/* Deprecated macros for SVE instructions */
>  
>  /* STR (vector): STR Z\nz, [X\nxbase, #\offset, MUL VL] */
>  .macro _sve_str_v nz, nxbase, offset=0
> -	_sve_check_zreg \nz
> -	_check_general_reg \nxbase
> -	_check_num (\offset), -0x100, 0xff
> -	.inst	0xe5804000			\
> -		| (\nz)				\
> -		| ((\nxbase) << 5)		\
> -		| (((\offset) & 7) << 10)	\
> -		| (((\offset) & 0x1f8) << 13)
> +	.arch_extension sve
> +	str	z\nz, [X\nxbase, #\offset, MUL VL]
>  .endm
>  
>  /* LDR (vector): LDR Z\nz, [X\nxbase, #\offset, MUL VL] */
>  .macro _sve_ldr_v nz, nxbase, offset=0
> -	_sve_check_zreg \nz
> -	_check_general_reg \nxbase
> -	_check_num (\offset), -0x100, 0xff
> -	.inst	0x85804000			\
> -		| (\nz)				\
> -		| ((\nxbase) << 5)		\
> -		| (((\offset) & 7) << 10)	\
> -		| (((\offset) & 0x1f8) << 13)
> +	.arch_extension sve
> +	ldr	z\nz, [X\nxbase, #\offset, MUL VL]
>  .endm
>  
>  /* STR (predicate): STR P\np, [X\nxbase, #\offset, MUL VL] */
>  .macro _sve_str_p np, nxbase, offset=0
> -	_sve_check_preg \np
> -	_check_general_reg \nxbase
> -	_check_num (\offset), -0x100, 0xff
> -	.inst	0xe5800000			\
> -		| (\np)				\
> -		| ((\nxbase) << 5)		\
> -		| (((\offset) & 7) << 10)	\
> -		| (((\offset) & 0x1f8) << 13)
> +	.arch_extension sve
> +	str	p\np, [X\nxbase, #\offset, MUL VL]
>  .endm
>  
>  /* LDR (predicate): LDR P\np, [X\nxbase, #\offset, MUL VL] */
>  .macro _sve_ldr_p np, nxbase, offset=0
> -	_sve_check_preg \np
> -	_check_general_reg \nxbase
> -	_check_num (\offset), -0x100, 0xff
> -	.inst	0x85800000			\
> -		| (\np)				\
> -		| ((\nxbase) << 5)		\
> -		| (((\offset) & 7) << 10)	\
> -		| (((\offset) & 0x1f8) << 13)
> +	.arch_extension sve
> +	ldr p\np, [x\nxbase, #\offset, MUL VL]
>  .endm
>  
>  /* RDVL X\nx, #\imm */
>  .macro _sve_rdvl nx, imm
> -	_check_general_reg \nx
> -	_check_num (\imm), -0x20, 0x1f
> -	.inst	0x04bf5000			\
> -		| (\nx)				\
> -		| (((\imm) & 0x3f) << 5)
> +	.arch_extension sve
> +	rdvl x\nx, #\imm
>  .endm
>  
>  /* RDFFR (unpredicated): RDFFR P\np.B */
>  .macro _sve_rdffr np
> -	_sve_check_preg \np
> -	.inst	0x2519f000			\
> -		| (\np)
> +	.arch_extension sve
> +	rdffr p\np\().b
>  .endm
>  
>  /* WRFFR P\np.B */
>  .macro _sve_wrffr np
> -	_sve_check_preg \np
> -	.inst	0x25289000			\
> -		| ((\np) << 5)
> +	.arch_extension sve
> +	wrffr p\np\().b
>  .endm
>  
>  /* PFALSE P\np.B */
>  .macro _sve_pfalse np
> -	_sve_check_preg \np
> -	.inst	0x2518e400			\
> -		| (\np)
> +	.arch_extension sve
> +	pfalse	p\np\().b
>  .endm
>  
>  /* SME instruction encodings for non-SME-capable assemblers */
> -- 2.30.2
> 

FWIW,

Reviewed-by: Vladimir Murzin <vladimir.murzin at arm.com>