[PATCH v7 1/2] dt-bindings: perf: marvell: Add CN20K DDR PMU binding

[Krzysztof Kozlowski]

On Wed, May 27, 2026 at 09:11:17PM +0530, Geetha sowjanya wrote:
> Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
> associated with the DDR controller. The block provides hardware counters
> to monitor DDR traffic and performance events and is accessed via a
> dedicated MMIO region.
> 
> The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with
> minor register offset differences.
> 
> Signed-off-by: Geetha sowjanya <gakula at marvell.com>
> ---
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at oss.qualcomm.com>

Best regards,
Krzysztof