[PATCH v10 02/30] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state

[Mark Brown]

On Tue, May 26, 2026 at 01:48:41PM +0100, Mark Rutland wrote:
> On Fri, Mar 06, 2026 at 05:00:54PM +0000, Mark Brown wrote:

> > We provide a helper which does the configuration as part of a
> > read/modify/write operation along with the configuration of the task VL,
> > then update the floating point state load and SME access trap to use it.

> > +		if (fa64)					\
> > +			__new |= SMCR_ELx_FA64;			\
> > +		if (zt0)					\
> > +			__new |= SMCR_ELx_EZT0;			\

> I'd strongly prefer that we make it the caller's responsiblity to track
> all the bits within SMCR, rather than requiring each caller to pass a
> bag of booleans.

I was explicitly going for the opposite of that in order to make it
harder for someone implementing a future extension to miss a place where
an update is required, having the callers independently constructing the
register values feels like it's asking for trouble.

> 	unsigned long __task_smcr(const struct task_struct *tsk)
> 	{
> 		unsigned long vq = sve_vq_from_vl(task_get_sme_vl(tsk));
> 		unsigned long smcr = vq - 1;

I agree that's a better pattern for the main kernel - we could also do
something similar with a task_set_smcr() which wraps the explicitly
specifed version.  That would I think avoid most of the issue you're
seeing?
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