[PATCH] arm64: tlb: Flush walk cache when unsharing PMD tables

[Zeng Heng]

Hi Catalin,

On 2026/5/22 18:38, Catalin Marinas wrote:
> On Fri, May 22, 2026 at 11:13:17AM +0100, Catalin Marinas wrote:
>> On Fri, May 22, 2026 at 01:32:07PM +0800, Zeng Heng wrote:
>>> On 2026/5/21 23:15, Catalin Marinas wrote:
>>>> On Thu, May 21, 2026 at 04:05:07PM +0100, Catalin Marinas wrote:
>>>>> On Thu, May 21, 2026 at 03:30:11PM +0800, Zeng Heng wrote:
>>>>>> From: Zeng Heng <zengheng4 at huawei.com>
>>>>>>
>>>>>> When huge_pmd_unshare() is called to unshare a PMD table, the
>>>>>> tlb_unshare_pmd_ptdesc() function sets tlb->unshared_tables=true
>>>>>> but the aarch64 tlb_flush() only checked tlb->freed_tables to
>>>>>> determine whether to use TLBF_NONE (vae1is, invalidates walk
>>>>>> cache) or TLBF_NOWALKCACHE (vale1is, leaf-only).
>>>>>>
>>>>>> This caused the stale PMD page table entry to remain in the walk cache
>>>>>> after unshare, potentially leading to incorrect page table walks.
>>>>>>
>>>>>> Fix by including unshared_tables in the check, so that when
>>>>>> unsharing tables, TLBF_NONE is used and the walk cache is properly
>>>>>> invalidated.
>>>>>>
>>>>>> Here is the detailed distinction between vae1is and vale1is:
>>>>>>
>>>>>> | Instruction Combination  | Actual Invalidation Scope                         |
>>>>>> | ------------------------ | --------------------------------------------------|
>>>>>> | `VAE1IS`  + TTL=`0`      | All entries at all levels (full invalidation)     |
>>>>>> | `VAE1IS`  + TTL=`2` (L2) | Non-leaf at Level 0/1 + leaf at Level 2           |
>>>>>> | `VALE1IS` + TTL=`0`      | Leaf entries at all levels (non-leaf not cleared) |
>>>>>> | `VALE1IS` + TTL=`2` (L2) | Leaf entry at Level 2 only                        |

To clarify, the above was confirmed internally with the Kunpeng team.

>>> Per the ARM Architecture Reference Manual, whether only the last-level
>>> page table entry is invalidated is determined by the instruction used
>>> (vale1is for leaf entry only, vae1is for walk cache including leaf entry and
>>> non-leaf entry), rather than the TTL field. The TTL field merely specifies
>>> which level the leaf entry belongs to.
>>
>> Ah, yes, you are right. The TTL is still 2 in this case for a huge pmd,
>> we just want the walk cache leading to it to be invalidated. So no need
>> for the additional tlb_get_level().
> 
> The Arm ARM is still unclear. The RVAE1IS has this wording:
> 
>    The TTL hint is only guaranteed to invalidate:
> 
>    - Non-leaf-level entries in the range up to but not including the
>      level described by the TTL hint.
> 
>    - Leaf-level entries in the range that match the level described by
>      the TTL hint.
> 
> But we don't have such wording around non-leaf-level entries for VAE1IS.
> I presume it would be the same but I'll ask internally next week. In the
> meantime, I'll take this patch.
> 

Got it. I agree the official ARM documentation doesn’t fully explain
this clearly.

Thanks for the additional confirmation.

Best regards,
Zeng Heng