[PATCH v2] arm: lpae: fix non-atomic page table entry update issue

[Wang YanQing]

On Sun, May 03, 2026 at 11:54:32PM +0800, Wang YanQing wrote:
> On Sun, Mar 15, 2026 at 01:12:28AM +0000, Russell King (Oracle) wrote:
> > On Sun, Mar 15, 2026 at 08:47:46AM +0800, Wang YanQing wrote:
> > > The ARM Architecture Reference Manual explicitly dictates that writes of 64-bit
> > > translation table descriptors must be single-copy atomic:
> > > ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition (https://developer.arm.com/documentation/ddi0406/latest)
> > > "
> > > ...
> > > A3.5.3 Atomicity in the ARM architecture
> > > ...
> > > In an implementation that includes the Large Physical Address Extension, LDRD, and STRD accesses to 64-bit aligned
> > > locations are 64-bit single-copy atomic as seen by translation table walks and accesses to translation tables.
> > > Note
> > > The Large Physical Address Extension adds this requirement to avoid the need for complex measures to avoid
> > > atomicity issues when changing translation table entries, without creating a requirement that all locations in the
> > > memory system are 64-bit single-copy atomic.
> > 
> > Thanks. Now, please locate where the need for the updates to the page
> > tables needs to be done atomically, bearing in mind that we program
> > SCTLR.AFE=1 and SCTLR.HA=0, meaning the hardware won't write-back to
> > the page tables to e.g. update the access flag.
> 
> Dear Russell and all
> 
> ARM Cortex-A cores (cortex-a7, cortex-a32, cortex-a55) all have "walk cache ram", 
> according to cortex_a32_trm_100241_0100_00_en.pdf (https://documentation-service.arm.com/static/5e7dca43cbfe76649ba52835)
> "
> ...
> The walk cache RAM holds the result of a stage 1 translation up to but not including the last
> level
> ...
> "
> 
> The walk cache ram will cache translation result of L1/L2 page table walk, so the non-atomic
> pmd entry update issue describe in the patch will cause partial updated 64-bit entry to be cached
> in the walk cache ram.
> 
> On SoCs like TI keystone and Sigmastar SoCs which will run arm32 linux kernel on high address,
> the physical address of page table will be 64-bit and will meet the issue described in the patch.
> 
> I think it is right to make page table entry update become atomic according to ARM Architecture 
> Reference Manual.
> 
> Thanks

Hi Linus and all

Non-atomic LPAE page table update issue on arm32 SOC that run linux kernel on hight address has 
caused strange mmu related problem, we meet strange unhandled prefetch abort issue due to the 
no-atomic update when we run arm32 linux on Sigmastar CA55 SoC that uses 0x10_0000_0000 as the 
start address of DRAM (We do the same thing as keystone SOC, use 0x2000_0000 as start address
of dram, then switch to high address)

I haven't get any respone from Russell King in last three months, the full history could be see
at: https://lkml.org/lkml/2026/3/15/38, I don't know why.
I think make the page table update become atomic is a proper solution for the problem according 
to ARM Architecture Reference Manual.

Because the mainline tipcode still has the problem, so I want to try again to make this patch 
become merged, if someone don't like it, please tell me what is the better solution for mainline
kernel.

Thanks.