[PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL clock controller

[Jian Hu]

On 5/22/2026 5:16 PM, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 22/05/2026 08:20, Jian Hu wrote:
>> Hi Krzysztof,
>>
>> Thanks for your review.
>>
>> On 5/15/2026 4:09 PM, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On Mon, May 11, 2026 at 08:47:24PM +0800, Jian Hu wrote:
>>>> Add the PLL clock controller dt-bindings for the Amlogic A9 SoC family.
>>>>
>>>> Signed-off-by: Jian Hu <jian.hu at amlogic.com>
>>>> ---
>>>>    .../bindings/clock/amlogic,a9-pll-clkc.yaml        | 110 +++++++++++++++++++++
>>>>    include/dt-bindings/clock/amlogic,a9-pll-clkc.h    |  55 +++++++++++
>>>>    2 files changed, 165 insertions(+)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
>>>> new file mode 100644
>>>> index 000000000000..4ee6013ba1a1
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml
>>>> @@ -0,0 +1,110 @@
>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>> +# Copyright (C) 2026 Amlogic, Inc. All rights reserved
>>>> +%YAML 1.2
>>>> +---
>>>> +$id: http://devicetree.org/schemas/clock/amlogic,a9-pll-clkc.yaml#
>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> +
>>>> +title: Amlogic A9 Series PLL Clock Controller
>>>> +
>>>> +maintainers:
>>>> +  - Neil Armstrong <neil.armstrong at linaro.org>
>>>> +  - Jerome Brunet <jbrunet at baylibre.com>
>>>> +  - Jian Hu <jian.hu at amlogic.com>
>>>> +  - Xianwei Zhao <xianwei.zhao at amlogic.com>
>>>> +
>>>> +properties:
>>>> +  compatible:
>>>> +    enum:
>>>> +      - amlogic,a9-gp0-pll
>>>> +      - amlogic,a9-hifi0-pll
>>>> +      - amlogic,a9-hifi1-pll
>>>> +      - amlogic,a9-mclk0-pll
>>>> +      - amlogic,a9-mclk1-pll
>>>> +
>>>> +  reg:
>>>> +    maxItems: 1
>>>> +
>>>> +  '#clock-cells':
>>>> +    const: 1
>>>> +
>>>> +  clocks:
>>>> +    items:
>>>> +      - description: pll input oscillator gate
>>>> +      - description: fixed input clock source for mclk_sel_0
>>>> +      - description: u3p2pll input clock source for mclk_sel_0 (optional)
>>> Second clock is also optional. Drop "(optional)" comment, just
>>> confusing.
>>
>> GP0 has only one parent clock, while MCLK has three.
>>
>> The second and third parent entries of GP0 are vacant,
>>
>> so they need to be marked optional.
>>
>> I will add the optional property for the second clock in the next revision.
> How? Read the previous feedback...
>
> Best regards,
> Krzysztof


My apologies, I misunderstood your previous comment.
I will drop "(optional)" from the clock descriptions.

It will be updated as:
   clocks:
     items:
       - description: pll input oscillator gate
       - description: fixed input clock source for mclk_sel_0
       - description: u3p2pll input clock source for mclk_sel_0


Best regards,

Jian