[PATCH v2 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms

Enric Balletbo i Serra eballetb at redhat.com
Thu May 21 08:40:48 PDT 2026


Hi Khristine,

Thank you to apply my reviews.

On Wed, May 20, 2026 at 5:10 PM Khristine Andreea Barbulescu
<khristineandreea.barbulescu at oss.nxp.com> wrote:
>
> Add the usbphynop node and the usbotg pinctrl
> support for the S32G2 and S32G3 SoCs.
>
> This enables the USB controller to reference the
> generic PHY and use the required pinmux for USB OTG ops.
>

I tried testing the patches, but unfortunately, they didn't work for
me on top of the current mainline. Any idea what could be wrong?

[   40.019850] usb_phy_generic usbphynop: dummy supplies not allowed
for exclusive requests (id=vbus)
[   40.268467] imx_usb 44064000.usb: No over current polarity defined
[   40.293272] ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1
[   40.308834] ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00
[   40.309475] usb usb1: New USB device found, idVendor=1d6b,
idProduct=0002, bcdDevice= 7.01
[   40.309485] usb usb1: New USB device strings: Mfr=3, Product=2,
SerialNumber=1
[   40.309492] usb usb1: Product: EHCI Host Controller
[   40.309498] usb usb1: Manufacturer: Linux 7.1.0-rc4+ ehci_hcd
[   40.309503] usb usb1: SerialNumber: ci_hdrc.0
[   40.311051] hub 1-0:1.0: USB hub found
[   40.748830] usb 1-1: new high-speed USB device number 2 using ci_hdrc
[   46.038582] usb 1-1: new full-speed USB device number 3 using ci_hdrc
[   61.347813] usb 1-1: device descriptor read/64, error -110
[   76.707030] usb 1-1: device descriptor read/64, error -110
[   76.817100] usb usb1-port1: attempt power cycle
[   77.256992] usb 1-1: new full-speed USB device number 4 using ci_hdrc
[   87.826466] usb 1-1: device not accepting address 4, error -110
[   87.956454] usb 1-1: new full-speed USB device number 5 using ci_hdrc
[   98.545933] usb 1-1: device not accepting address 5, error -110
[   98.546070] usb usb1-port1: unable to enumerate USB device

It looks like a problem with the ULPI communication because I cannot
read the ULPI registers.

Thanks,
   Enric


> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu at oss.nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi      |  7 ++-
>  arch/arm64/boot/dts/freescale/s32g3.dtsi      |  7 ++-
>  .../boot/dts/freescale/s32gxxxa-evb.dtsi      | 46 ++++++++++++++++++-
>  .../boot/dts/freescale/s32gxxxa-rdb.dtsi      | 46 ++++++++++++++++++-
>  4 files changed, 102 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..a35bb284270e 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
>   * NXP S32G2 SoC family
>   *
>   * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
>   */
>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -108,6 +108,11 @@ psci {
>                 };
>         };
>
> +       usbphynop: usbphynop {
> +               compatible = "usb-nop-xceiv";
> +               #phy-cells = <0>;
> +       };
> +
>         soc at 0 {
>                 compatible = "simple-bus";
>                 #address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d..b980e5f2b059 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
>   *
>   * Authors: Ghennadi Procopciuc <ghennadi.procopciuc at nxp.com>
>   *          Ciprian Costea <ciprianmarian.costea at nxp.com>
> @@ -165,6 +165,11 @@ scmi_shmem: shm at d0000000 {
>                 };
>         };
>
> +       usbphynop: usbphynop {
> +               compatible = "usb-nop-xceiv";
> +               #phy-cells = <0>;
> +       };
> +
>         soc at 0 {
>                 compatible = "simple-bus";
>                 #address-cells = <1>;
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> index 803ff4531077..26009c1e90dc 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2024 NXP
> + * Copyright 2024, 2026 NXP
>   *
>   * Authors: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
>   *          Ghennadi Procopciuc <ghennadi.procopciuc at oss.nxp.com>
> @@ -245,6 +245,39 @@ dspi5-grp4 {
>                         bias-pull-up;
>                 };
>         };
> +
> +       usbotg_pins: usbotg-pins {
> +               usbotg-grp0 {
> +                       pinmux = <0x3802>, <0x3812>,
> +                               <0x3822>, <0x3832>,
> +                               <0x3842>, <0x3852>,
> +                               <0x3862>, <0x3872>,
> +                               <0x37f2>, <0x3882>,
> +                               <0x3892>;
> +               };
> +
> +               usbotg-grp1 {
> +                       pinmux = <0x3e1>, <0x3f1>,
> +                               <0x401>, <0x411>,
> +                               <0xbc1>, <0xbd1>,
> +                               <0xbe1>, <0x701>;
> +                       output-enable;
> +                       input-enable;
> +                       slew-rate = <208>;
> +               };
> +
> +               usbotg-grp2 {
> +                       pinmux = <0xb80>, <0xb90>, <0xbb0>;
> +                       input-enable;
> +                       slew-rate = <208>;
> +               };
> +
> +               usbotg-grp3 {
> +                       pinmux = <0xba1>;
> +                       output-enable;
> +                       slew-rate = <208>;
> +               };
> +       };
>  };
>
>  &can0 {
> @@ -304,3 +337,14 @@ &spi5 {
>         pinctrl-names = "default";
>         status = "okay";
>  };
> +
> +&usbmisc {
> +       status = "okay";
> +};
> +
> +&usbotg {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&usbotg_pins>;
> +       phys = <&usbphynop>;
> +       status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> index 979868f6d2c5..a8abb10b0e7a 100644
> --- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2024 NXP
> + * Copyright 2024, 2026 NXP
>   *
>   * Authors: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
>   *          Ghennadi Procopciuc <ghennadi.procopciuc at oss.nxp.com>
> @@ -199,6 +199,39 @@ dspi5-grp4 {
>                         bias-pull-up;
>                 };
>         };
> +
> +       usbotg_pins: usbotg-pins {
> +               usbotg-grp0 {
> +                       pinmux = <0x3802>, <0x3812>,
> +                               <0x3822>, <0x3832>,
> +                               <0x3842>, <0x3852>,
> +                               <0x3862>, <0x3872>,
> +                               <0x37f2>, <0x3882>,
> +                               <0x3892>;
> +               };
> +
> +               usbotg-grp1 {
> +                       pinmux = <0x3e1>, <0x3f1>,
> +                               <0x401>, <0x411>,
> +                               <0xbc1>, <0xbd1>,
> +                               <0xbe1>, <0x701>;
> +                       output-enable;
> +                       input-enable;
> +                       slew-rate = <208>;
> +               };
> +
> +               usbotg-grp2 {
> +                       pinmux = <0xb80>, <0xb90>, <0xbb0>;
> +                       input-enable;
> +                       slew-rate = <208>;
> +               };
> +
> +               usbotg-grp3 {
> +                       pinmux = <0xba1>;
> +                       output-enable;
> +                       slew-rate = <208>;
> +               };
> +       };
>  };
>
>  &can0 {
> @@ -257,3 +290,14 @@ &i2c4 {
>         pinctrl-1 = <&i2c4_gpio_pins>;
>         status = "okay";
>  };
> +
> +&usbmisc {
> +       status = "okay";
> +};
> +
> +&usbotg {
> +       pinctrl-names = "default";
> +       pinctrl-0 = <&usbotg_pins>;
> +       phys = <&usbphynop>;
> +       status = "okay";
> +};
> --
> 2.34.1
>




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