[PATCH v8 1/5] dt-bindings: clock: airoha: Add PHY binding for Serdes port

[Krzysztof Kozlowski]

On Wed, May 20, 2026 at 05:09:06PM +0200, Christian Marangi wrote:
> Add PHY cell property for Serdes port selection. Currently supported only
> for Airoha AN7581 SoC, that support up to 4 Serdes port.
> 
> The Serdes port can support both PCIe, USB3 or Ethernet mode.
> 
> - PCIe1 Serdes can support PCIe or Ethernet mode.
> - PCIe2 Serdes can support PCIe or Ethernet mode.
> - USB1 Serdes can support USB3 or HSGMII mode.
> - USB2 Serdes can support USB3 or PCIe mode.
> 
> Add bindings to permit correct reference of the Serdes ports in DT.
> Values are just symbolic and enumerates the Serdes port with a specific
> number for precise reference.
> 
> The available Serdes port can be selected following the dt-binding header
> in [2].
> 
> [2] <include/dt-bindings/soc/airoha,scu-ssr.h>
> 
> Signed-off-by: Christian Marangi <ansuelsmth at gmail.com>
> ---
>  .../devicetree/bindings/clock/airoha,en7523-scu.yaml  |  9 +++++++++
>  include/dt-bindings/soc/airoha,scu-ssr.h              | 11 +++++++++++
>  2 files changed, 20 insertions(+)
>  create mode 100644 include/dt-bindings/soc/airoha,scu-ssr.h

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at oss.qualcomm.com>

Best regards,
Krzysztof