[PATCH 03/10] dt-bindings: clock: Add Amlogic A9 peripherals clock controller

[Jian Hu]

Hi Jerome,

Thanks for your review.

On 5/15/2026 12:15 AM, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
> On lun. 11 mai 2026 at 20:47, Jian Hu via B4 Relay <devnull+jian.hu.amlogic.com at kernel.org> wrote:
>
>> From: Jian Hu <jian.hu at amlogic.com>
>>
>> Add the peripherals clock controller dt-bindings for the Amlogic A9
>> SoC family.
>>
>> Signed-off-by: Jian Hu <jian.hu at amlogic.com>
>> ---
>>   .../clock/amlogic,a9-peripherals-clkc.yaml         | 150 +++++++++
>>   .../clock/amlogic,a9-peripherals-clkc.h            | 352 +++++++++++++++++++++
>>   2 files changed, 502 insertions(+)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
>> b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
>> new file mode 100644
>> index 000000000000..97e2c44d8630
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-peripherals-clkc.yaml
>> @@ -0,0 +1,150 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +# Copyright (C) 2026 Amlogic, Inc. All rights reserved
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/clock/amlogic,a9-peripherals-clkc.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Amlogic A9 Series Peripherals Clock Controller
>> +
>> +maintainers:
>> +  - Neil Armstrong <neil.armstrong at linaro.org>
>> +  - Jerome Brunet <jbrunet at baylibre.com>
>> +  - Jian Hu <jian.hu at amlogic.com>
>> +  - Xianwei Zhao <xianwei.zhao at amlogic.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: amlogic,a9-peripherals-clkc
>> +
>> +  reg:
>> +    maxItems: 1
>> +
>> +  '#clock-cells':
>> +    const: 1
>> +
>> +  clocks:
>> +    minItems: 20
>> +    items:
>> +      - description: input oscillator
>> +      - description: input fclk div 2
>> +      - description: input fclk div 3
>> +      - description: input fclk div 4
>> +      - description: input fclk div 5
>> +      - description: input fclk div 7
>> +      - description: input fclk div 2p5
>> +      - description: input sys clk
>> +      - description: input gp1 pll
>> +      - description: input gp2 pll
>> +      - description: input sys pll div 16
>> +      - description: input cpu clk div 16
>> +      - description: input a78 clk div 16
>> +      - description: input dsu clk div 16
>> +      - description: input rtc clk
>> +      - description: input gp0 pll
>> +      - description: input hifi0 pll
>> +      - description: input hifi1 pll
>> +      - description: input mclk0 pll
>> +      - description: input mclk1 pll
>> +      - description: input video1 pll (optional)
>> +      - description: input video2 pll (optional)
>> +      - description: input hdmi out2 clk (optional)
>> +      - description: input hdmi pixel clk (optional)
>> +      - description: input pixel0 pll (optional)
>> +      - description: input pixel1 pll (optional)
>> +      - description: input usb2 drd clk (optional)
> Why are those optional ? they seem internal to the SoC.
> If so, they don't have a reason to be optional


Yes , these clocks are sourced from other analog modules and will be 
added in the future.

I will remove the optional in the next version.

>> +      - description: external input rmii oscillator (optional)
>> +
[...]
> --
> Jerome

Best regards,

Jian