[PATCH v2 1/1] arm64: dts: s32g: add SAR ADC support for s32g2 and s32g3

[Enric Balletbo i Serra]

Hi,

On Thu, May 14, 2026 at 10:26 AM Khristine Andreea Barbulescu
<khristineandreea.barbulescu at oss.nxp.com> wrote:
>
> Add ADC0 and ADC1 for S32G2 and S32G3 SoCs.
>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu at oss.nxp.com>

Reviewed-by: Enric Balletbo i Serra <eballetb at redhat.com>

Thanks,
   Enric

> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 22 +++++++++++++++++++++-
>  arch/arm64/boot/dts/freescale/s32g3.dtsi | 22 +++++++++++++++++++++-
>  2 files changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..6f1952fbbcfe 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
>   * NXP S32G2 SoC family
>   *
>   * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
>   */
>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -554,6 +554,16 @@ i2c2: i2c at 401ec000 {
>                         status = "disabled";
>                 };
>
> +               adc0: adc at 401f8000 {
> +                       compatible = "nxp,s32g2-sar-adc";
> +                       reg = <0x401f8000 0x1000>;
> +                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 0x41>;
> +                       dmas = <&edma0 0 32>;
> +                       dma-names = "rx";
> +                       status = "disabled";
> +               };
> +
>                 swt4: watchdog at 40200000 {
>                         compatible = "nxp,s32g2-swt";
>                         reg = <0x40200000 0x1000>;
> @@ -717,6 +727,16 @@ i2c4: i2c at 402dc000 {
>                         status = "disabled";
>                 };
>
> +               adc1: adc at 402e8000 {
> +                       compatible = "nxp,s32g2-sar-adc";
> +                       reg = <0x402e8000 0x1000>;
> +                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 0x41>;
> +                       dmas = <&edma1 1 32>;
> +                       dma-names = "rx";
> +                       status = "disabled";
> +               };
> +
>                 usdhc0: mmc at 402f0000 {
>                         compatible = "nxp,s32g2-usdhc";
>                         reg = <0x402f0000 0x1000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d..5cfb37c1216a 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
>   *
>   * Authors: Ghennadi Procopciuc <ghennadi.procopciuc at nxp.com>
>   *          Ciprian Costea <ciprianmarian.costea at nxp.com>
> @@ -617,6 +617,16 @@ i2c2: i2c at 401ec000 {
>                         status = "disabled";
>                 };
>
> +               adc0: adc at 401f8000 {
> +                       compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
> +                       reg = <0x401f8000 0x1000>;
> +                       interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 0x41>;
> +                       dmas = <&edma0 0 32>;
> +                       dma-names = "rx";
> +                       status = "disabled";
> +               };
> +
>                 swt4: watchdog at 40200000 {
>                         compatible = "nxp,s32g3-swt", "nxp,s32g2-swt";
>                         reg = <0x40200000 0x1000>;
> @@ -792,6 +802,16 @@ i2c4: i2c at 402dc000 {
>                         status = "disabled";
>                 };
>
> +               adc1: adc at 402e8000 {
> +                       compatible = "nxp,s32g3-sar-adc", "nxp,s32g2-sar-adc";
> +                       reg = <0x402e8000 0x1000>;
> +                       interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 0x41>;
> +                       dmas = <&edma1 1 32>;
> +                       dma-names = "rx";
> +                       status = "disabled";
> +               };
> +
>                 usdhc0: mmc at 402f0000 {
>                         compatible = "nxp,s32g3-usdhc",
>                                      "nxp,s32g2-usdhc";
> --
> 2.34.1
>