[PATCH v2 1/1] arm64: dts: s32g: add PIT support for s32g2 and s32g3

[Enric Balletbo i Serra]

Hi,

Somewhat related I'd appreciate a review to:

https://lore.kernel.org/all/20260514-fix-nxp-timer-v3-1-a3e68fdb505e@redhat.com/

The changes looks good to me, so

On Mon, May 18, 2026 at 8:36 AM Khristine Andreea Barbulescu
<khristineandreea.barbulescu at oss.nxp.com> wrote:
>
> Add PIT0 and PIT1 for S32G2 and S32G3 SoCs
>
> Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu at oss.nxp.com>

Reviewed-by: Enric Balletbo i Serra <eballetb at redhat.com>

Thanks,
   Enric

> ---
>  arch/arm64/boot/dts/freescale/s32g2.dtsi | 20 +++++++++++++++++++-
>  arch/arm64/boot/dts/freescale/s32g3.dtsi | 20 +++++++++++++++++++-
>  2 files changed, 38 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 51d00dac12de..57ff97e44507 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -3,7 +3,7 @@
>   * NXP S32G2 SoC family
>   *
>   * Copyright (c) 2021 SUSE LLC
> - * Copyright 2017-2021, 2024-2025 NXP
> + * Copyright 2017-2021, 2024-2026 NXP
>   */
>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -417,6 +417,15 @@ edma0: dma-controller at 40144000 {
>                         clock-names = "dmamux0", "dmamux1";
>                 };
>
> +               pit0: pit at 40188000 {
> +                       compatible = "nxp,s32g2-pit";
> +                       reg = <0x40188000 0x3000>;
> +                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 61>;
> +                       clock-names = "pit";
> +                       status = "disabled";
> +               };
> +
>                 can0: can at 401b4000 {
>                         compatible = "nxp,s32g2-flexcan";
>                         reg = <0x401b4000 0xa000>;
> @@ -622,6 +631,15 @@ edma1: dma-controller at 40244000 {
>                         clock-names = "dmamux0", "dmamux1";
>                 };
>
> +               pit1: pit at 40288000 {
> +                       compatible = "nxp,s32g2-pit";
> +                       reg = <0x40288000 0x3000>;
> +                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 61>;
> +                       clock-names = "pit";
> +                       status = "disabled";
> +               };
> +
>                 can2: can at 402a8000 {
>                         compatible = "nxp,s32g2-flexcan";
>                         reg = <0x402a8000 0xa000>;
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index e314f3c7d61d..efe5398e1240 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -1,6 +1,6 @@
>  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
>  /*
> - * Copyright 2021-2025 NXP
> + * Copyright 2021-2026 NXP
>   *
>   * Authors: Ghennadi Procopciuc <ghennadi.procopciuc at nxp.com>
>   *          Ciprian Costea <ciprianmarian.costea at nxp.com>
> @@ -475,6 +475,15 @@ edma0: dma-controller at 40144000 {
>                         clock-names = "dmamux0", "dmamux1";
>                 };
>
> +               pit0: pit at 40188000 {
> +                       compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
> +                       reg = <0x40188000 0x3000>;
> +                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 61>;
> +                       clock-names = "pit";
> +                       status = "disabled";
> +               };
> +
>                 can0: can at 401b4000 {
>                         compatible = "nxp,s32g3-flexcan",
>                                            "nxp,s32g2-flexcan";
> @@ -693,6 +702,15 @@ edma1: dma-controller at 40244000 {
>                         clock-names = "dmamux0", "dmamux1";
>                 };
>
> +               pit1: pit at 40288000 {
> +                       compatible = "nxp,s32g3-pit", "nxp,s32g2-pit";
> +                       reg = <0x40288000 0x3000>;
> +                       interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
> +                       clocks = <&clks 61>;
> +                       clock-names = "pit";
> +                       status = "disabled";
> +               };
> +
>                 can2: can at 402a8000 {
>                         compatible = "nxp,s32g3-flexcan",
>                                            "nxp,s32g2-flexcan";
> --
> 2.34.1
>