[PATCH v2 0/3] ARM: dts: aspeed: anacapa: restructure devicetree for development-phase
Andrew Jeffery
andrew at codeconstruct.com.au
Mon May 18 05:05:12 PDT 2026
Hi Colin,
Firstly, apologies that it's taken some time for me to get to this.
Next, thanks for taking on-board the idea of separating the
devicetrees. I have some comments on that below, as I think we could
improve on what you've proposed.
On Thu, 2026-04-09 at 19:40 +0800, Colin Huang wrote:
> This series refactors the Anacapa BMC devicetree layout to better support
> development-phase hardware revisions (EVT1/EVT2) while keeping a platform
> entrypoint.
>
> Signed-off-by: Colin Huang <u8813345 at gmail.com>
> ---
> Changes in v2:
> - Fix dtbs_check fail.
> Validated by following command:
> make dt_binding_check DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml
> make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa.dtb
> make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt1.dtb
> make CHECK_DTBS=y DT_SCHEMA_FILES=arm/aspeed/aspeed.yaml aspeed/aspeed-bmc-facebook-anacapa-evt2.dtb
> - Link to v1: https://lore.kernel.org/r/20260407-anacapa-devlop-phase-devicetree-v1-0-97b96367cac3@gmail.com
>
> ---
> Colin Huang (3):
> dt-bindings: arm: aspeed: add Anacapa EVT1 EVT2 board
> ARM: dts: aspeed: anacapa: add EVT1 devicetree and point wrapper to it
> ARM: dts: aspeed: anacapa: add EVT2 devicetree and update wrapper
>
> .../devicetree/bindings/arm/aspeed/aspeed.yaml | 2 +
> .../aspeed/aspeed-bmc-facebook-anacapa-evt1.dts | 1067 +++++++++++++++++++
> .../aspeed/aspeed-bmc-facebook-anacapa-evt2.dts | 1123 ++++++++++++++++++++
So it appears you've copy/pasted the evt1 content into evt2. Taking the
diff between them we see mainly changes to GPIO names. I've pasted the
diff below for reference.
I think it would be rather more succinct and maintainable to include
the evt1 dts then override the gpio-line-names properties in evt2 for
the relevant devices.
Similarly for the root compatible and the extra I2C EEPROM.
--- aspeed-bmc-facebook-anacapa-evt1.dts 2026-05-18 21:23:03.480670629 +0930
+++ aspeed-bmc-facebook-anacapa-evt2.dts 2026-05-18 21:23:03.532671920 +0930
@@ -7,7 +7,7 @@
/ {
model = "Facebook Anacapa BMC";
- compatible = "facebook,anacapa-bmc-evt1", "aspeed,ast2600";
+ compatible = "facebook,anacapa-bmc-evt2", "aspeed,ast2600";
aliases {
serial0 = &uart1;
@@ -129,8 +129,8 @@
sck-gpios = <&gpio0 ASPEED_GPIO(Z, 3) GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio0 ASPEED_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio0 ASPEED_GPIO(Z, 5) GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
num-chipselects = <1>;
+ cs-gpios = <&gpio0 ASPEED_GPIO(Z, 0) GPIO_ACTIVE_LOW>;
status = "okay";
tpm at 0 {
@@ -193,11 +193,15 @@
"","","","","","","","",
/*B0-B7*/
- "BATTERY_DETECT", "", "", "BMC_READY",
- "", "FM_ID_LED", "", "",
+ "BATTERY_DETECT", "",
+ "BMC_I2C1_FPGA_ALERT", "BMC_READY",
+ "IOEXP_INT_3V3", "FM_ID_LED",
+ "", "",
/*C0-C7*/
- "","","","","","","","",
+ "","","","",
+ "PMBUS_REQ_N", "PSU_FW_UPDATE_REQ_N",
+ "", "",
/*D0-D7*/
"","","","","","","","",
@@ -209,15 +213,17 @@
"","","","","","","","",
/*G0-G7*/
- "FM_MUX1_SEL", "", "", "",
- "", "", "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
+ "FM_MUX1_SEL", "",
+ "", "", "", "",
+ "FM_DEBUG_PORT_PRSNT_N", "FM_BMC_DBP_PRESENT_N",
/*H0-H7*/
"","","","","","","","",
/*I0-I7*/
- "", "", "", "",
- "", "FLASH_WP_STATUS", "BMC_JTAG_MUX_SEL", "",
+ "","","","",
+ "", "FLASH_WP_STATUS",
+ "BMC_JTAG_MUX_SEL", "",
/*J0-J7*/
"","","","","","","","",
@@ -229,29 +235,46 @@
"","","","","","","","",
/*M0-M7*/
- "", "BMC_FRU_WP", "", "",
- "", "", "", "",
+ "PCIE_EP_RST_EN", "BMC_FRU_WP",
+ "SCM_HPM_STBY_RST_N", "SCM_HPM_STBY_EN",
+ "STBY_POWER_PG_3V3", "TH500_SHDN_OK",
+ "", "",
/*N0-N7*/
- "LED_POSTCODE_0", "LED_POSTCODE_1", "LED_POSTCODE_2", "LED_POSTCODE_3",
- "LED_POSTCODE_4", "LED_POSTCODE_5", "LED_POSTCODE_6", "LED_POSTCODE_7",
+ "LED_POSTCODE_0", "LED_POSTCODE_1",
+ "LED_POSTCODE_2", "LED_POSTCODE_3",
+ "LED_POSTCODE_4", "LED_POSTCODE_5",
+ "LED_POSTCODE_6", "LED_POSTCODE_7",
/*O0-O7*/
- "","","","","","","","",
+ "RUN_POWER_PG", "PWR_BRAKE",
+ "CHASSIS_AC_LOSS", "BSM_PRSNT_N",
+ "PSU_SMB_ALERT", "FM_TPM_PRSNT_0_N",
+ "PSU_FW_UPDATING_N", "",
/*P0-P7*/
- "PWR_BTN_BMC_BUF_N", "", "ID_RST_BTN_BMC_N", "",
- "PWR_LED", "", "", "BMC_HEARTBEAT_N",
+ "PWR_BTN_BMC_BUF_N", "IPEX_CABLE_PRSNT",
+ "ID_RST_BTN_BMC_N", "RST_BMC_RSTBTN_OUT_N",
+ "PWR_LED", "RUN_POWER_EN",
+ "SHDN_FORCE", "BMC_HEARTBEAT_N",
/*Q0-Q7*/
- "","","","","","","","",
+ "IRQ_PCH_TPM_SPI_LV3_N", "USB_OC0_REAR_N",
+ "UART_MUX_SEL", "I2C_MUX_RESET",
+ "RSVD_NV_PLT_DETECT", "SPI_TPM_INT",
+ "CPU_JTAG_MUX_SELECT", "THERM_BB_OVERT",
/*R0-R7*/
- "","","","","","","","",
+ "THERM_BB_WARN", "SPI_BMC_FPGA_INT",
+ "CPU_BOOT_DONE", "PMBUS_GNT",
+ "CHASSIS_PWR_BRK", "PCIE_WAKE",
+ "PDB_THERM_OVERT", "SHDN_REQ",
/*S0-S7*/
- "", "", "SYS_BMC_PWRBTN_N", "",
- "", "", "", "RUN_POWER_FAULT",
+ "", "",
+ "SYS_BMC_PWRBTN_N", "FM_TPM_PRSNT_1_N",
+ "FM_BMC_DEBUG_SW_N", "UID_LED_N",
+ "SYS_FAULT_LED_N", "RUN_POWER_FAULT",
/*T0-T7*/
"","","","","","","","",
@@ -260,7 +283,10 @@
"","","","","","","","",
/*V0-V7*/
- "","","","","","","","",
+ "L2_RST_REQ_OUT", "L0L1_RST_REQ_OUT",
+ "BMC_ID_BEEP_SEL", "BMC_I2C0_FPGA_ALERT",
+ "SMB_BMC_TMP_ALERT", "PWR_LED_N",
+ "SYS_RST_OUT", "IRQ_TPM_SPI_N",
/*W0-W7*/
"","","","","","","","",
@@ -269,11 +295,12 @@
"","","","","","","","",
/*Y0-Y7*/
- "","","","","","","","",
+ "RST_WDTRST_PLD_N", "RST_BMC_SELF_HW",
+ "FM_FLASH_LATCH_N", "BMC_EMMC_RST_N",
+ "","","","",
/*Z0-Z7*/
- "SPI_BMC_TPM_CS2_N", "", "", "SPI_BMC_TPM_CLK",
- "SPI_BMC_TPM_MOSI", "SPI_BMC_TPM_MISO", "", "";
+ "","","","","","","","";
};
&gpio1 {
@@ -287,7 +314,8 @@
"FM_BOARD_BMC_REV_ID2", "",
/*18C0-18C7*/
- "","","","","","","","",
+ "", "", "SPI_BMC_BIOS_ROM_IRQ0_N", "",
+ "", "", "", "",
/*18D0-18D7*/
"","","","","","","","",
@@ -586,6 +614,11 @@
reg = <0x50>;
};
+ eeprom at 51 {
+ compatible = "atmel,24c128";
+ reg = <0x51>;
+ };
+
// BSM FRU
eeprom at 56 {
compatible = "atmel,24c64";
@@ -862,89 +895,106 @@
ngpios = <128>;
bus-frequency = <2000000>;
gpio-line-names =
- /*in - out - in - out */
+ /*in - out */
/* A0-A7 line 0-15 */
- "", "FM_CPU0_SYS_RESET_N", "", "CPU0_KBRST_N",
- "", "FM_CPU0_PROCHOT_trigger_N", "", "FM_CLR_CMOS_R_P0",
- "", "Force_I3C_SEL", "", "SYSTEM_Force_Run_AC_Cycle",
- "", "", "", "",
+ "L_FNIC_FLT", "FM_CPU0_SYS_RESET_N",
+ "L_BNIC0_FLT", "CPU0_KBRST_N",
+ "L_BNIC1_FLT", "FM_CPU0_PROCHOT_trigger_N",
+ "L_BNIC2_FLT", "FM_CLR_CMOS_R_P0",
+ "L_BNIC3_FLT", "Force_I3C_SEL",
+ "L_RTM_SW_FLT", "SYSTEM_Force_Run_AC_Cycle",
+ "", "",
+ "", "",
/* B0-B7 line 16-31 */
"Channel0_leakage_EAM3", "FM_CPU_FPGA_JTAG_MUX_SEL",
"Channel1_leakage_EAM0", "FM_SCM_JTAG_MUX_SEL",
"Channel2_leakage_Manifold1", "FM_BRIDGE_JTAG_MUX_SEL",
"Channel3_leakage", "FM_CPU0_NMI_SYNC_FLOOD_N",
- "Channel4_leakage_Manifold2", "",
- "Channel5_leakage_EAM1", "",
- "Channel6_leakage_CPU_DIMM", "",
- "Channel7_leakage_EAM2", "",
+ "Channel4_leakage_Manifold2", "BMC_AINIC0_WP_R2_L",
+ "Channel5_leakage_EAM1", "BMC_AINIC1_WP_R2_L",
+ "Channel6_leakage_CPU_DIMM", "CPLD_BUF_R_AGPIO330",
+ "Channel7_leakage_EAM2", "CPLD_BUF_R_AGPIO331",
/* C0-C7 line 32-47 */
- "RSVD_RMC_GPIO3", "", "", "",
- "", "", "", "",
- "LEAK_DETECT_RMC_N", "", "", "",
- "", "", "", "",
+ "RSVD_RMC_GPIO3", "RTM_MUX_L",
+ "LEAK_DETECT_RMC_N", "RTM_MUX_R",
+ "HDR_P0_NMI_BTN_BUF_R_N", "FPGA_JTAG_SCM_DBREQ_N",
+ "No_Leak_Sensor_flag", "whdt_sel",
+ "", "",
+ "", "",
+ "", "",
+ "", "",
/* D0-D7 line 48-63 */
- "PWRGD_PDB_EAMHSC0_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC1_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC2_CPLD_PG_R", "",
- "PWRGD_PDB_EAMHSC3_CPLD_PG_R", "",
- "AMC_BRD_PRSNT_CPLD_L", "", "", "",
- "", "", "", "",
+ "PWRGD_CHAD_CPU0_FPGA", "",
+ "PWRGD_CHEH_CPU0_FPGA", "",
+ "PWRGD_CHIL_CPU0_FPGA", "",
+ "PWRGD_CHMP_CPU0_FPGA", "",
+ "AMC_BRD_PRSNT_CPLD_L", "",
+ "", "",
+ "", "",
+ "", "",
/* E0-E7 line 64-79 */
- "AMC_PDB_EAMHSC0_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC1_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC2_CPLD_EN_R", "",
- "AMC_PDB_EAMHSC3_CPLD_EN_R", "",
- "", "", "", "",
- "", "", "", "",
+ "L_PRSNT_B_FENIC_R2_N", "",
+ "L_PRSNT_B_BENIC0_R2_N", "",
+ "L_PRSNT_B_BENIC1_R2_N", "",
+ "L_PRSNT_B_BENIC2_R2_N", "",
+ "L_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
/* F0-F7 line 80-95 */
- "PWRGD_PVDDCR_CPU1_P0", "SGPIO_READY",
- "PWRGD_PVDDCR_CPU0_P0", "",
- "", "", "", "",
- "", "", "", "",
+ "R_PRSNT_B_FENIC_R2_N", "SGPIO_READY",
+ "R_PRSNT_B_BENIC0_R2_N", "",
+ "R_PRSNT_B_BENIC1_R2_N", "",
+ "R_PRSNT_B_BENIC2_R2_N", "",
+ "R_PRSNT_B_BENIC3_R2_N", "",
+ "", "",
+ "", "",
+ "", "",
/* G0-G7 line 96-111 */
- "PWRGD_PVDDCR_SOC_P0", "",
- "PWRGD_PVDDIO_P0", "",
- "PWRGD_PVDDIO_MEM_S3_P0", "",
- "PWRGD_CHMP_CPU0_FPGA", "",
- "PWRGD_CHIL_CPU0_FPGA", "",
- "PWRGD_CHEH_CPU0_FPGA", "",
- "PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
+ "L_PRSNT_EDSFF2_N", "",
+ "L_PRSNT_EDSFF3_N", "",
+ "R_PRSNT_EDSFF2_N", "",
+ "R_PRSNT_EDSFF3_N", "",
+ "", "",
"", "",
+ "", "",
+ "PRSNT_NFC_BOARD_R", "",
/* H0-H7 line 112-127 */
- "PWRGD_P3V3", "",
- "P12V_DDR_IP_PWRGD_R", "",
- "P12V_DDR_AH_PWRGD_R", "",
- "PWRGD_P12V_VRM1_CPLD_PG_R", "",
- "PWRGD_P12V_VRM0_CPLD_PG_R", "",
- "PWRGD_PDB_HSC4_CPLD_PG_R", "",
- "PWRGD_PVDD18_S5_P0_PG", "",
- "PWRGD_PVDD33_S5_P0_PG", "",
+ "R_FNIC_FLT", "",
+ "R_BNIC0_FLT", "",
+ "R_BNIC1_FLT", "",
+ "R_BNIC2_FLT", "",
+ "R_BNIC3_FLT", "",
+ "R_RTM_SW_FLT", "",
+ "", "",
+ "", "",
/* I0-I7 line 128-143 */
"EAM0_BRD_PRSNT_R_L", "",
"EAM1_BRD_PRSNT_R_L", "",
"EAM2_BRD_PRSNT_R_L", "",
"EAM3_BRD_PRSNT_R_L", "",
- "EAM0_CPU_MOD_PWR_GD_R", "",
- "EAM1_CPU_MOD_PWR_GD_R", "",
- "EAM2_CPU_MOD_PWR_GD_R", "",
- "EAM3_CPU_MOD_PWR_GD_R", "",
+ "FM_TPM_PRSNT_R_N", "",
+ "PDB_PRSNT_R_N", "",
+ "PRSNT_EDSFF0_N", "",
+ "PRSNT_CPU0_N", "",
/* J0-J7 line 144-159 */
- "PRSNT_L_BIRDGE_R", "",
- "PRSNT_R_BIRDGE_R", "",
+ "PRSNT_L_BRIDGE_R", "",
+ "PRSNT_R_BRIDGE_R", "",
"BRIDGE_L_MAIN_PG_R", "",
"BRIDGE_R_MAIN_PG_R", "",
"BRIDGE_L_STBY_PG_R", "",
"BRIDGE_R_STBY_PG_R", "",
- "", "", "", "",
+ "IRQ_NFC_BOARD_R", "",
+ "RSMRST_N", "",
/* K0-K7 line 160-175 */
"ADC_I2C_ALERT_N", "",
@@ -957,10 +1007,14 @@
"PDB_ALERT_R_N", "",
/* L0-L7 line 176-191 */
- "CPU0_SP7R1", "", "CPU0_SP7R2", "",
- "CPU0_SP7R3", "", "CPU0_SP7R4", "",
- "CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
- "CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
+ "CPU0_SP7R1", "",
+ "CPU0_SP7R2", "",
+ "CPU0_SP7R3", "",
+ "CPU0_SP7R4", "",
+ "CPU0_CORETYPE0", "",
+ "CPU0_CORETYPE1", "",
+ "CPU0_CORETYPE2", "",
+ "FM_BIOS_POST_CMPLT_R_N", "",
/* M0-M7 line 192-207 */
"EAM0_SMERR_CPLD_R_L", "",
@@ -978,27 +1032,29 @@
"AMC_STBY_PGOOD_R", "",
"CPU_AMC_SLP_S5_R_L", "",
"AMC_CPU_EAMPG_R", "",
- "", "", "", "",
+ "DIMM_PMIC_PG_TIMEOUT", "",
+ "EAM_MOD_PWR_GD_TIMEOUT", "",
+ "CPLD_AMC_STBY_PWR_EN", "",
/* O0-O7 line 224-239 */
"HPM_PWR_FAIL", "Port80_b0",
"FM_DIMM_IP_FAIL", "Port80_b1",
"FM_DIMM_AH_FAIL", "Port80_b2",
"HPM_AMC_THERMTRIP_R_L", "Port80_b3",
- "FM_CPU0_THERMTRIP_N", "Port80_b4",
+ "cpu_thermtrip_detect", "Port80_b4",
"PVDDCR_SOC_P0_OCP_L", "Port80_b5",
"CPLD_SGPIO_RDY", "Port80_b6",
- "", "Port80_b7",
+ "FM_MAIN_PWREN_RMC_EN_ISO", "Port80_b7",
/* P0-P7 line 240-255 */
"CPU0_SLP_S5_N_R", "NFC_VEN",
"CPU0_SLP_S3_N_R", "",
"FM_CPU0_PWRGD", "",
"PWRGD_RMC", "",
- "FM_RST_CPU0_RESET_N", "",
- "FM_PWRGD_CPU0_PWROK", "",
- "wS5_PWR_Ready", "",
- "wS0_ON_N", "PWRGD_P1V0_AUX";
+ "FM_RST_CPU0_RESET_N", "RBB_CPLD_RISCV_RST",
+ "FM_PWRGD_CPU0_PWROK", "LBB_CPLD_RISCV_RST",
+ "AMC_FAIL", "HPM_CPLD_RISCV_RST",
+ "wS0_ON_N", "";
status = "okay";
};
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