[PATCH] ARM: dts: aspeed: anacapa: name EDSFF and thermtrip SGPIO lines

[Andrew Jeffery]

Hello Rex,

On Thu, 2026-04-30 at 13:44 +0800, Rex Fu via B4 Relay wrote:
> From: Rex Fu <Rex.Fu at amd.com>
> 
> Name the Anacapa SGPIO lines used for EDSFF power-good and thermtrip
> assertion signals.
> 
> The affected lines replace legacy
> 

Which are legacy?

>  or unused 
> 

Which are unused?

> CPU-related names with the
> platform signal names used by userspace monitoring.

This is the kind of change that has the potential to break old
userspace. Why is it appropriate? I'd like a more precise discussion in
the commit message.

Was there some other underlying change (e.g. a new revision of the
platform design)?

Andrew

> 
> Signed-off-by: Rex Fu <Rex.Fu at amd.com>
> ---
>  arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> index 2cb7bd128d24..fe960bb7bc27 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-anacapa.dts
> @@ -912,7 +912,7 @@ &sgpiom0 {
>  	"PWRGD_PVDDIO_P0", "",
>  	"PWRGD_PVDDIO_MEM_S3_P0", "",
>  	"PWRGD_CHMP_CPU0_FPGA", "",
> -	"PWRGD_CHIL_CPU0_FPGA", "",
> +	"HPM_EDSFF_PG", "",
>  	"PWRGD_CHEH_CPU0_FPGA", "",
>  	"PWRGD_CHAD_CPU0_FPGA", "FM_BMC_READY_PLD",
>  	"", "",
> @@ -957,8 +957,8 @@ &sgpiom0 {
>  	"PDB_ALERT_R_N", "",
>  
>  	/* L0-L7 line 176-191 */
> -	"CPU0_SP7R1", "", "CPU0_SP7R2", "",
> -	"CPU0_SP7R3", "", "CPU0_SP7R4", "",
> +	"L_EDSFF2_PG", "", "L_EDSFF3_PG", "",
> +	"R_EDSFF2_PG", "", "R_EDSFF3_PG", "",
>  	"CPU0_CORETYPE0", "", "CPU0_CORETYPE1", "",
>  	"CPU0_CORETYPE2", "", "FM_BIOS_POST_CMPLT_R_N", "",
>  
> @@ -984,8 +984,8 @@ &sgpiom0 {
>  	"HPM_PWR_FAIL", "Port80_b0",
>  	"FM_DIMM_IP_FAIL", "Port80_b1",
>  	"FM_DIMM_AH_FAIL", "Port80_b2",
> -	"HPM_AMC_THERMTRIP_R_L", "Port80_b3",
> -	"FM_CPU0_THERMTRIP_N", "Port80_b4",
> +	"AMC_THERMTRIP_ASSERT", "Port80_b3",
> +	"CPU_THERMTRIP_ASSERT", "Port80_b4",
>  	"PVDDCR_SOC_P0_OCP_L", "Port80_b5",
>  	"CPLD_SGPIO_RDY", "Port80_b6",
>  	"", "Port80_b7",
> 
> ---
> base-commit: 9974969c14031a097d6b45bcb7a06bb4aa525c40
> change-id: 20260430-anacapa-sgpio-edsff-thermtrip-acb228bf61be
> 
> Best regards,
> --  
> Rex Fu <Rex.Fu at amd.com>
>