[PATCH 1/1] arm64: dts: Add usbphynop and usbotg pinctrl for S32G platforms

[Khristine Andreea Barbulescu]

Add the usbphynop node and the usbotg pinctrl
support for the S32G2 and S32G3 SoCs.

This enables the USB controller to reference the
generic PHY and use the required pinmux for USB OTG ops.

Signed-off-by: Khristine Andreea Barbulescu <khristineandreea.barbulescu at oss.nxp.com>
---
 .../boot/dts/freescale/s32gxxxa-evb.dtsi      | 53 ++++++++++++++++++-
 .../boot/dts/freescale/s32gxxxa-rdb.dtsi      | 53 ++++++++++++++++++-
 2 files changed, 104 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
index 803ff4531077..d096744cdb0f 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-evb.dtsi
@@ -1,12 +1,19 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2024 NXP
+ * Copyright 2024, 2026 NXP
  *
  * Authors: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
  *          Ghennadi Procopciuc <ghennadi.procopciuc at oss.nxp.com>
  *          Larisa Grigore <larisa.grigore at nxp.com>
  */
 
+/ {
+	usbphynop: usbphynop {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+};
+
 &pinctrl {
 	can0_pins: can0-pins {
 		can0-grp0 {
@@ -245,6 +252,39 @@ dspi5-grp4 {
 			bias-pull-up;
 		};
 	};
+
+	usbotg_pins: usbotg_pins {
+		usbotg_grp0 {
+			pinmux = <0x3802>, <0x3812>,
+				<0x3822>, <0x3832>,
+				<0x3842>, <0x3852>,
+				<0x3862>, <0x3872>,
+				<0x37f2>, <0x3882>,
+				<0x3892>;
+		};
+
+		usbotg_grp1 {
+			pinmux = <0x3e1>, <0x3f1>,
+				<0x401>, <0x411>,
+				<0xbc1>, <0xbd1>,
+				<0xbe1>, <0x701>;
+			output-enable;
+			input-enable;
+			slew-rate = <208>;
+		};
+
+		usbotg_grp2 {
+			pinmux = <0xb80>, <0xb90>, <0xbb0>;
+			input-enable;
+			slew-rate = <208>;
+		};
+
+		usbotg_grp3 {
+			pinmux = <0xba1>;
+			output-enable;
+			slew-rate = <208>;
+		};
+	};
 };
 
 &can0 {
@@ -304,3 +344,14 @@ &spi5 {
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&usbmisc {
+	status = "okay";
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usbotg_pins>;
+	fsl,usbphy = <&usbphynop>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
index 979868f6d2c5..b756bcf6469d 100644
--- a/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32gxxxa-rdb.dtsi
@@ -1,12 +1,19 @@
 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 /*
- * Copyright 2024 NXP
+ * Copyright 2024, 2026 NXP
  *
  * Authors: Ciprian Marian Costea <ciprianmarian.costea at oss.nxp.com>
  *          Ghennadi Procopciuc <ghennadi.procopciuc at oss.nxp.com>
  *          Larisa Grigore <larisa.grigore at nxp.com>
  */
 
+/ {
+	usbphynop: usbphynop {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
+};
+
 &pinctrl {
 	can0_pins: can0-pins {
 		can0-grp0 {
@@ -199,6 +206,39 @@ dspi5-grp4 {
 			bias-pull-up;
 		};
 	};
+
+	usbotg_pins: usbotg_pins {
+		usbotg_grp0 {
+			pinmux = <0x3802>, <0x3812>,
+				<0x3822>, <0x3832>,
+				<0x3842>, <0x3852>,
+				<0x3862>, <0x3872>,
+				<0x37f2>, <0x3882>,
+				<0x3892>;
+		};
+
+		usbotg_grp1 {
+			pinmux = <0x3e1>, <0x3f1>,
+				<0x401>, <0x411>,
+				<0xbc1>, <0xbd1>,
+				<0xbe1>, <0x701>;
+			output-enable;
+			input-enable;
+			slew-rate = <208>;
+		};
+
+		usbotg_grp2 {
+			pinmux = <0xb80>, <0xb90>, <0xbb0>;
+			input-enable;
+			slew-rate = <208>;
+		};
+
+		usbotg_grp3 {
+			pinmux = <0xba1>;
+			output-enable;
+			slew-rate = <208>;
+		};
+	};
 };
 
 &can0 {
@@ -257,3 +297,14 @@ &i2c4 {
 	pinctrl-1 = <&i2c4_gpio_pins>;
 	status = "okay";
 };
+
+&usbmisc {
+	status = "okay";
+};
+
+&usbotg {
+	pinctrl-names = "default";
+	pinctrl-0 = <&usbotg_pins>;
+	fsl,usbphy = <&usbphynop>;
+	status = "okay";
+};
-- 
2.34.1