[PATCH] clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs

[Krzysztof Kozlowski]

On Tue, 05 May 2026 17:14:57 +0000, Kuan-Wei Chiu wrote:
> In the peric0_clk_regs array, the divider register offset for USI6 was
> accidentally listed twice, while the divider for USI7 was omitted.
> 
> Missing this DIV register causes the USI7 clock divider setting to be
> lost and reset to its hardware default value during a suspend/resume
> cycle.
> 
> [...]

Applied, thanks!

[1/1] clk: samsung: gs101: Fix missing USI7_USI DIV clock in peric0_clk_regs
      https://git.kernel.org/krzk/linux/c/78ee734b36284d82454e87a92094fdb926985b47

Best regards,
-- 
Krzysztof Kozlowski <krzk at kernel.org>